[Intel-gfx] 3d driver

I use opensuse(12.1) Linux. toshiba laptop, Intel i5 processor, 4gb ram, intel hd graphics In KDE, sys info shows===> 2d driver-- intel, 3d driver unknown (classic7.11) But in Gnome 3.2, sys info shows ===> graphics ===> Intel Sandybridge mobile X86/MMX/ SSE 2. I am using only KDE, what is th

Re: [Intel-gfx] [PATCH 08/25] drm/i915: ValleyView mode setting limits and PLL functions

On Wed, 21 Mar 2012 12:48:29 -0700 Jesse Barnes wrote: > From: Vijay Purushothaman > > Add some VLV limit structures and update the PLL code. > > Signed-off-by: Shobhit Kumar > Signed-off-by: Vijay Purushothaman > --- > drivers/gpu/drm/i915/i915_reg.h |1 + > drivers/gpu/drm/i915/i

Re: [Intel-gfx] [PATCH 05/25] drm/i915: add DPIO read/write functions for ValleyView

On Wed, 21 Mar 2012 12:48:26 -0700 Jesse Barnes wrote: > ValleyView and similar hardware (like CedarView) put some display > related registers like the PLL controls and dividers on a DPIO bus. Add > simple indirect register access routines to get to those registers. > > Signed-off-by: Jesse Bar

[Intel-gfx] [PATCH 26/37] drm/i915: reuse Ivybridge interrupts code for Haswell

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_irq.c |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index afd4e03..ede51f0 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/dr

[Intel-gfx] [PATCH 24/37] drm/i915: share forcewaking code between IVB and HSW

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 24a0a6c..27ab70d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b

[Intel-gfx] [PATCH 35/37] drm/i915: program iCLKIP on Lynx Point

The iCLKIP clock is used to drive the VGA pixel clock on the PCH. In order to do so, it must be programmed to properly do the clock ticks according to the divisor, phase direction, phase increments and a special auxiliary divisor for 20MHz clock. Those values can be programmed individually, by doi

[Intel-gfx] [PATCH 19/37] drm/i915: add LCPLL control registers

Those are used to control the display core clock. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 03fb10d..fa9e3a8 100644 --- a/drivers/gpu/drm/

[Intel-gfx] [PATCH 18/37] drm/i915: add GTC registers

Add Global Time Clock registers Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 193fb11..03fb10d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++

[Intel-gfx] [PATCH 29/37] drm/i915: enable power wells on haswell init

This attempts to enable all the available power wells during the initialization. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i

[Intel-gfx] [PATCH 13/37] drm/i915: add support for SBI ops

With Lynx Point, we need to use SBI to communicate with the display clock control. This commit adds helper functions to access the registers via SBI. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 44 ++ 1 file changed, 44 insertions(+)

[Intel-gfx] [PATCH 30/37] drm/i915: disable rc6 on haswell for now

This needs proper enablement to avoid machine hangs, so let's just avoid it for now. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c inde

[Intel-gfx] [PATCH 11/37] drm/i915: add definition of DDI buffer translations regs

Those registers are used to train DDI buffer translations for each link type. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b732aa1..0af47b4 1

[Intel-gfx] [PATCH 28/37] drm/i915: share IVB cursor routine with Haswell

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2978597..3b3dc15 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b

[Intel-gfx] [PATCH 33/37] drm/i915: double-write DDI translation table

Some double-buffered registers need to be written twice. Note that it is being sent as a separate patch because sometimes these registers do work when written only once. But double-writing on my machine ensured that they work more often. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH 25/37] drm/i915: haswell has 3 pipes as well

They work differently, but the count is the same. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_dma.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 9341eb8..a2c0e75 100644 --- a/drivers

[Intel-gfx] [PATCH 27/37] drm/i915: share pipe count handling with Ivybridge

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 27ab70d..2978597 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b

[Intel-gfx] [PATCH 10/37] drm/i915: add definition of LPT FDI port width registers

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2927460..b732aa1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @

[Intel-gfx] [PATCH 20/37] drm/i915: add WM_LINETIME registers

Watermark line time registers for display low power watermark. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fa9e3a8..76f7acb 100644 --- a

[Intel-gfx] [PATCH 12/37] drm/i915: add SBI registers

Those are responsible for the Sideband Interface programming. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0af47b4..4ee8965 100644 --- a/

[Intel-gfx] [PATCH 31/37] drm/i915: enable PCH earlier

The modesetting sequence for PCH-related connections mentions that the order of plane/pipe enablement could happen either before of after PCH enablement. With LPT, however, we need to enable some things earlier to be able to talk to PCH. So let's do it a bit in advance. Signed-off-by: Eugeni Dodo

[Intel-gfx] [PATCH 21/37] drm/i915: calculate watermarks on Gen7 archs in one place

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c225de4..46633fe 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b

[Intel-gfx] [PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell

We don't have those bits on Haswell anymore, so do not set them. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e

[Intel-gfx] [PATCH 16/37] drm/i915: add port clock selection support for HSW

Multiple clocks can drive different outputs. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e38dafc..eebe9d3 100644 --- a/driv

[Intel-gfx] [PATCH 22/37] drm/i915: program WM_LINETIME on Haswell

The line time can be programmed according to the number of horizontal pixels vs effective pixel rate ratio. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gp

[Intel-gfx] [PATCH 14/37] drm/i915: add PIXCLK_GATE register

Pixel clock gating control for Lynx point. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4ee8965..9ff9856 100644 --- a/drivers/gpu/drm/i915/i91

[Intel-gfx] [PATCH 37/37] drm/i915: dump registers read/write ops

This logs all the registers and SBI accesses as they happen. Note that it is not supposed to go into the final patch series. But there are too many subtle changes in both HSW and LPT that are much easier to spot with this extra debugging when attaching a dmesg output in case of problems. In other

[Intel-gfx] [PATCH 17/37] drm/i915: add SSC offsets for SBI access

Different registers are identified by their target id and offset. To simplify their programming, they are called as . For example, SSCCTL register accessed through SBI at target id 6 and offset 0c is called SBI_SSCCTL6. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 15 +++

[Intel-gfx] [PATCH 15/37] drm/i915: add S PLL control

This PLL control can drive DDI ports at desired frequencies for DisplayPort and FDI connections. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h inde

[Intel-gfx] [PATCH 34/37] drm/i915: do not use fdi_normal_train on haswell

This should be already configured when FDI auto-negotiation is done. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index

[Intel-gfx] [PATCH 32/37] drm/i915: perform Haswell DDI link training in FDI mode

This patch attempts at following the modeset sequence closely, retrying with different voltages if the DP_TP_STATUS reports a failed training. For training, we add a table of recommended settings for FDI, HDMI and DP connections. For FDI and DP modes, we also add the HDMI buffer translation as the

[Intel-gfx] [PATCH 36/37] drm/i915: add warning when using old bits on Haswell/LPT

Those have different functionality on Haswell architecture, so let's trigger a warning message when we are going through a path we should not go into on Haswell. This patch is here for make debugging and log tracing easier, it should go away in the future, we we'll stop hitting those code paths.

Re: [Intel-gfx] [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block

On Wed, 21 Mar 2012 12:48:25 -0700 Jesse Barnes wrote: > From: Rohit Jain > > Added support for parsing the OEM Customizable Modes Block (#20) > in the VBIOS table. > > Signed-off-by: Rohit Jain > Reviewed-by: Shobhit Kumar > Reviewed-by: Vijay A. Purushothaman > Acked-by: Jesse Barnes > R

Re: [Intel-gfx] [PATCH 03/25] drm/i915: re-order GT IIR bit definitions

On Wed, 21 Mar 2012 12:48:24 -0700 Jesse Barnes wrote: > They were all over the place, order them by position and add a few. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_reg.h | 20 ++-- > 1 files changed, 14 insertions(+), 6 deletions(-) > > diff --git

[Intel-gfx] [PATCH 09/37] drm/i915: add definitions for DDI_BUF_CTL registers

There is one instance of those registers for each DDI port. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3831fe7..2927460 10

[Intel-gfx] [PATCH 08/37] drm/i915: add DP_TP_STATUS registers

There is one set of those registers for each port. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7a9232e..3831fe7 100644 --- a/drivers/gpu/dr

[Intel-gfx] [PATCH 07/37] drm/i915: add DP_TP_CTL registers

This is one set of those registers for each pipe. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 09b2267..7a9232e 100644 --- a/driver

[Intel-gfx] [PATCH 06/37] drm/i915: add DDI registers

There is one set of such registers for each pipe (A/B/C/EDP). Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 27 +++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ddc9c87..09b2

[Intel-gfx] [PATCH 05/37] drm/i915: add support for power wells

This defines the registers used by different power wells. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 52a06be..ddc9c87 100644 --- a/d

[Intel-gfx] [PATCH 04/37] drm/i915: add haswell into the PCH SPLIT company

Haswell is similar to Ivy Bridge in this sense. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_drv.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fb50c42..51e04ec 100644 --- a/drivers/g

[Intel-gfx] [PATCH 03/37] drm/i915: add HAS_PLL_SPLIT macro

Ivy Bridge is the only GPU which has split 3-display support over 2 PLLs. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_drv.h |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 49488e1..fb50c42 100644 --- a

[Intel-gfx] [PATCH 02/37] drm/i915: add support for LynxPoint PCH

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_drv.c |4 drivers/gpu/drm/i915/i915_drv.h |2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index d4f542b..5fe9d62 100644 --- a/drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 01/37] drm/i915: add Haswell devices and their PCI IDs

This adds product definitions for desktop, mobile and server boards. Signed-off-by: Eugeni Dodonov --- drivers/char/agp/intel-agp.c|4 drivers/char/agp/intel-agp.h| 11 +++ drivers/char/agp/intel-gtt.c| 14 ++ drivers/gpu/drm/i915/i915_drv.c | 23 ++

[Intel-gfx] [RFC] [PATCH 00/38] Haswell

Hi folks, To contribute to everyones curiosity and further enrich Phoronix articles :), this is the initial Haswell enablement patchset for basic modesetting support over VGA. This is actually the first time I am doing such enablement, and the combination of HSW/LPT changes proved to be quite tri

Re: [Intel-gfx] [PATCH 02/25] drm/i915: add debug message when EDID fetch fails

On Wed, 21 Mar 2012 13:53:12 -0700 Jesse Barnes wrote: > On Wed, 21 Mar 2012 17:44:12 -0300 > Eugeni Dodonov wrote: > > > On Wed, Mar 21, 2012 at 16:48, Jesse Barnes > > wrote: > > > > > + } else { > > > > + DRM_DEBUG_KMS("failed to fetch edid\n"); > > >} > > > > >

[Intel-gfx] [PATCH 2/2] drm/i915: use semaphores for the display plane

In theory this will have performance and power improvements. Performance because we don't need to stall when the scanout BO is busy, and power because we don't have to stall when the BO is busy ie. we can get the work done sooner and put the CPU to sleep (and one less interrupt required). Signed-o

[Intel-gfx] [PATCH 1/2] drm/i915: extract ring sync code

We want to use this function elsewhere... Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_drv.h| 19 + drivers/gpu/drm/i915/i915_gem.c| 43 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 60 +--- 3 files c

[Intel-gfx] [PATCH 0/2] semaphorify the pageflip BO (if possible)

I've not observed any FPS changes with my limited testing. Here is the performance data I collected with nexuiz, measuring the latency of i915_gem_object_pin_to_display_plane. Top is before, bottom is after. N Min MaxMedian AvgStddev x 2246

[Intel-gfx] [PATCH] drm/i915: properly restore the ppgtt page directory on resume

The ppgtt page directory lives in a snatched part of the gtt pte range. Which naturally gets cleared on hibernate when we pull the power. Suspend to ram (which is what I've tested) works because despite the fact that this is a mmio region, it is actually back by system ram. Fix this by moving the

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check VBIOS value for determining LVDS dual channel mode, too

On Tue, Mar 20, 2012 at 01:07:05PM +0100, Takashi Iwai wrote: > Currently i915 driver checks [PCH_]LVDS register bits to decide > whether to set up the dual-link or the single-link mode. This relies > implicitly on that BIOS initializes the register properly at boot. > However, BIOS doesn't initia

Re: [Intel-gfx] [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions

On Wed, 21 Mar 2012 17:55:58 -0400 Adam Jackson wrote: > On Wed, 2012-03-21 at 14:32 -0700, Jesse Barnes wrote: > > > We need force wake, just not for any parts I've tested yet (the early > > ones had the Punit disabled). > > > > This code adheres to the spec, but I'll need a part with the Puni

Re: [Intel-gfx] [PATCH 25/25] drm/i915: don't write ring regs until they're set up

On Wed, 21 Mar 2012 22:46:41 +0100 Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 12:48:46PM -0700, Jesse Barnes wrote: > > intel_clear_scanline_wait tries to clear ring wait conditions when we > > turn off pipes, to prevent hanging WAIT_EVENT and similar commands. But > > we call it early befor

Re: [Intel-gfx] [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions

On Wed, 2012-03-21 at 14:32 -0700, Jesse Barnes wrote: > We need force wake, just not for any parts I've tested yet (the early > ones had the Punit disabled). > > This code adheres to the spec, but I'll need a part with the Punit > enabled in order to test & verify. Until then we can leave it di

Re: [Intel-gfx] [PATCH 22/25] drm/i915: remove some unneeded debug messages

On Wed, 21 Mar 2012 22:36:22 +0100 Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 12:48:43PM -0700, Jesse Barnes wrote: > > Signed-off-by: Jesse Barnes > > So you've achieved the contentless-error-msg nirvana? Luckily for you one > of these is quality work from China ;-) Patch applied to next,

Re: [Intel-gfx] [RFC] ValleyView support

On Wed, Mar 21, 2012 at 12:48:21PM -0700, Jesse Barnes wrote: > In this set, you can see why I was asking about register offsets and > splitting the display code. Included are a few cleanups to help me keep > my sanity, but as I mentioned in my other mail I think we should go > further. > > Many

Re: [Intel-gfx] [PATCH 09/25] drm/915: program driain latency regs on ValleyView

On Wed, 2012-03-21 at 22:00 +0100, Daniel Vetter wrote: > Bikeshed, but imo important: Can we make the unimportant part in these > function names less noise and instead make the interesting part readable? > I.e. s/valleyview/vlv/ and s/dl/drain_latency or drain_lat Honestly I'd be in favor of tha

Re: [Intel-gfx] [PATCH 25/25] drm/i915: don't write ring regs until they're set up

On Wed, Mar 21, 2012 at 12:48:46PM -0700, Jesse Barnes wrote: > intel_clear_scanline_wait tries to clear ring wait conditions when we > turn off pipes, to prevent hanging WAIT_EVENT and similar commands. But > we call it early before rings have been setup during initialization and > shouldn't touc

Re: [Intel-gfx] [PATCH 24/25] drm/i915: add has_turbo bit to driver info struct

On Wed, Mar 21, 2012 at 12:48:45PM -0700, Jesse Barnes wrote: > Since ValleyView is a gen7 chip but doesn't have the same turbo interface. > > Signed-off-by: Jesse Barnes Commit headline is imo misleading - effectively the patch disables turbo on vlv. Then msg body could then elaborate that we d

Re: [Intel-gfx] [PATCH 23/25] drm/i915: add ValleyView clock gating init

On Wed, Mar 21, 2012 at 12:48:44PM -0700, Jesse Barnes wrote: > Set the same bits as IVB plus a few others. > > Signed-off-by: Jesse Barnes Minor patch order request: Can you move that to the wm stuff where this function gets added? -Daniel > --- > drivers/gpu/drm/i915/i915_reg.h | 18 +

Re: [Intel-gfx] [PATCH 22/25] drm/i915: remove some unneeded debug messages

On Wed, Mar 21, 2012 at 10:36:22PM +0100, Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 12:48:43PM -0700, Jesse Barnes wrote: > > Signed-off-by: Jesse Barnes > > So you've achieved the contentless-error-msg nirvana? Luckily for you one > of these is quality work from China ;-) Patch applied to n

Re: [Intel-gfx] [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView

On Wed, 21 Mar 2012 22:33:43 +0100 Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 12:48:40PM -0700, Jesse Barnes wrote: > > Although internally the MMIO offsets for display regs haven't changed, > > their visibility through the PCI BAR has been affected by the addition > > of the Gunit, which occ

Re: [Intel-gfx] [PATCH 22/25] drm/i915: remove some unneeded debug messages

On Wed, Mar 21, 2012 at 12:48:43PM -0700, Jesse Barnes wrote: > Signed-off-by: Jesse Barnes So you've achieved the contentless-error-msg nirvana? Luckily for you one of these is quality work from China ;-) Patch applied to next, thanks. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c |

Re: [Intel-gfx] [PATCH 17/25] drm/i915: ValleyView cacheability is different

On Wed, 21 Mar 2012 22:19:36 +0100 Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 12:48:38PM -0700, Jesse Barnes wrote: > > The GT can snoop CPU writes, but doesn't snoop into the CPU cache when > > it does writes, so we can't use the cache bits the same way. > > > > So map the status and pipe c

Re: [Intel-gfx] [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView

On Wed, Mar 21, 2012 at 12:48:40PM -0700, Jesse Barnes wrote: > Although internally the MMIO offsets for display regs haven't changed, > their visibility through the PCI BAR has been affected by the addition > of the Gunit, which occupies the low part of the address space. > > Display regs on VLV

Re: [Intel-gfx] [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions

On Wed, 21 Mar 2012 22:11:25 +0100 Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 12:48:37PM -0700, Jesse Barnes wrote: > > ValleyView handles force wake differently than previous chipsets, so add > > a couple of new functions for it. > > > > But it's also untested, so no need to call these unte

Re: [Intel-gfx] [PATCH 07/25] drm/i915: split out DPLL update code from i9xx_crtc_mode_set

On Wed, 21 Mar 2012 21:55:55 +0100 Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 12:48:28PM -0700, Jesse Barnes wrote: > > ValleyView needs something different here, and it cleans up the function > > quite a bit. > > > > Signed-off-by: Jesse Barnes > > Signed-off-by: Artem Bityutskiy > > Sign

Re: [Intel-gfx] [PATCH 14/25] agp/intel: always use uncached mappings on VLV

On Wed, Mar 21, 2012 at 10:09:18PM +0100, Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 12:48:35PM -0700, Jesse Barnes wrote: > > Until the snoopable ones are debugged. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/char/agp/intel-gtt.c |3 +-- > > 1 files changed, 1 insertions(+),

Re: [Intel-gfx] [PATCH 17/25] drm/i915: ValleyView cacheability is different

On Wed, Mar 21, 2012 at 12:48:38PM -0700, Jesse Barnes wrote: > The GT can snoop CPU writes, but doesn't snoop into the CPU cache when > it does writes, so we can't use the cache bits the same way. > > So map the status and pipe control pages as uncached on ValleyView, and > only set the pages to

Re: [Intel-gfx] [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions

On Wed, Mar 21, 2012 at 12:48:37PM -0700, Jesse Barnes wrote: > ValleyView handles force wake differently than previous chipsets, so add > a couple of new functions for it. > > But it's also untested, so no need to call these untested functions yet. > > Signed-off-by: Jesse Barnes So we have fo

Re: [Intel-gfx] [PATCH 14/25] agp/intel: always use uncached mappings on VLV

On Wed, Mar 21, 2012 at 12:48:35PM -0700, Jesse Barnes wrote: > Until the snoopable ones are debugged. > > Signed-off-by: Jesse Barnes > --- > drivers/char/agp/intel-gtt.c |3 +-- > 1 files changed, 1 insertions(+), 2 deletions(-) > > diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char

Re: [Intel-gfx] [PATCH 13/25] agp/intel: add Valleyview specific PTE entry function

On Wed, Mar 21, 2012 at 12:48:34PM -0700, Jesse Barnes wrote: > On VLV we need to flush the TLBs of the Gunit when updating PTEs. We > could put this off until we've written a whole block of entries, but we > don't currently have a nice place to put that. > > Signed-off-by: Jesse Barnes > --- >

Re: [Intel-gfx] [PATCH 12/25] agp/intel: map more registers for use by the GTT code

On Wed, Mar 21, 2012 at 12:48:33PM -0700, Jesse Barnes wrote: > We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the > register for doing so is above the range we normally map. Map the whole > register space to make sure we can get it. > > Signed-off-by: Jesse Barnes > --- > d

Re: [Intel-gfx] [PATCH 11/25] drm/i915: Enable HDMI on ValleyView

On Wed, Mar 21, 2012 at 12:48:32PM -0700, Jesse Barnes wrote: > From: Shobhit Kumar > > HDMI register offsets are different in Valleyview. Add support for the > same. > > Signed-off-by: Beeresh G > Signed-off-by: Shobhit Kumar > Reviewed-by: Vijay Purushothaman > Reviewed-by: Jesse Barnes >

Re: [Intel-gfx] [PATCH 09/25] drm/915: program driain latency regs on ValleyView

On Wed, Mar 21, 2012 at 12:48:30PM -0700, Jesse Barnes wrote: > From: Gajanan Bhat > > This patch adds support for programming drain latency registers of Pondicherry > memory arbiter of Valleyview. s/driain/drain in the subject. I've read drisomething and got momentarily confused. > > Signed-o

Re: [Intel-gfx] [PATCH 07/25] drm/i915: split out DPLL update code from i9xx_crtc_mode_set

On Wed, Mar 21, 2012 at 12:48:28PM -0700, Jesse Barnes wrote: > ValleyView needs something different here, and it cleans up the function > quite a bit. > > Signed-off-by: Jesse Barnes > Signed-off-by: Artem Bityutskiy > Signed-off-by: Jesse Barnes Simply resending the patch doesn't make it bet

Re: [Intel-gfx] [PATCH 02/25] drm/i915: add debug message when EDID fetch fails

On Wed, 21 Mar 2012 17:44:12 -0300 Eugeni Dodonov wrote: > On Wed, Mar 21, 2012 at 16:48, Jesse Barnes wrote: > > > + } else { > > + DRM_DEBUG_KMS("failed to fetch edid\n"); > >} > > > > > Wouldn't it be prettier if we also add some: >... >err = -ENXIO; >

Re: [Intel-gfx] [PATCH 06/25] drm/i915: add ValleyView registers, stub code, and watermark support

On Wed, Mar 21, 2012 at 12:48:27PM -0700, Jesse Barnes wrote: > ValleyView is a CedarView-like chip but with an Ivybridge graphics core. > This patch adds initial framework for supporting this chip. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_drv.c | 21 + >

Re: [Intel-gfx] [PATCH 02/25] drm/i915: add debug message when EDID fetch fails

On Wed, Mar 21, 2012 at 16:48, Jesse Barnes wrote: > + } else { + DRM_DEBUG_KMS("failed to fetch edid\n"); >} > Wouldn't it be prettier if we also add some: ... err = -ENXIO; or similar error in that block, to let the caller know that we failed as well? >

Re: [Intel-gfx] RFC: i915 arch changes to better support new chipsets

On Tue, 20 Mar 2012 13:13:47 -0700 Jesse Barnes wrote: > > > I'm open to suggestions on how to fix i915_reg.h; it's becoming quite a > > > beast. Our goal to be to make it easy to add new definitions while > > > also making it easy to not accidentally use old an incorrect > > > definitions on a n

Re: [Intel-gfx] [PATCH 01/25] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c

On Wed, Mar 21, 2012 at 16:48, Jesse Barnes wrote: > It's only used by the main read/write functions, so we can keep it with > them. > > Signed-off-by: Jesse Barnes > Reviewed-by: Eugeni Dodonov (One patch less from my own series to send). -- Eugeni Dodonov _

[Intel-gfx] [PATCH 15/25] drm/i915: add ValleyView specific CRT detect function

Might be able to merge this back in at some point, but we're seeing bugs with ADPA based detection, so keep it separate for now with explicit hotplug trigger usage. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_crt.c | 40 ++ 1 files changed, 40

[Intel-gfx] [PATCH 14/25] agp/intel: always use uncached mappings on VLV

Until the snoopable ones are debugged. Signed-off-by: Jesse Barnes --- drivers/char/agp/intel-gtt.c |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 8d5bef3..25911a1 100644 --- a/drivers/char/agp/intel-gt

[Intel-gfx] [PATCH 17/25] drm/i915: ValleyView cacheability is different

The GT can snoop CPU writes, but doesn't snoop into the CPU cache when it does writes, so we can't use the cache bits the same way. So map the status and pipe control pages as uncached on ValleyView, and only set the pages to cached if we're on a supported platform. Signed-off-by: Jesse Barnes -

[Intel-gfx] [PATCH 25/25] drm/i915: don't write ring regs until they're set up

intel_clear_scanline_wait tries to clear ring wait conditions when we turn off pipes, to prevent hanging WAIT_EVENT and similar commands. But we call it early before rings have been setup during initialization and shouldn't touch the ring regs yet. Signed-off-by: Jesse Barnes --- drivers/gpu/dr

[Intel-gfx] [PATCH 18/25] drm/i915: ValleyView IRQ support

ValleyView has a new interrupt architecture; best to put it in a new set of functions. Also make sure the ring mask functions handle ValleyView. FIXME: fix flipping; need to enable interrupts and call prepare/finish Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_debugfs.c | 40

[Intel-gfx] [PATCH 20/25] drm/i915: check for disabled interrupts on ValleyView

Haven't seen this yet, but it doesn't hurt. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_gem.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1f441f5..f47a28b 100644 --- a/drivers/gpu/

[Intel-gfx] [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView

Although internally the MMIO offsets for display regs haven't changed, their visibility through the PCI BAR has been affected by the addition of the Gunit, which occupies the low part of the address space. Display regs on VLV are offset into the BAR by 0x18, so we need to add that for any disp

[Intel-gfx] [PATCH 13/25] agp/intel: add Valleyview specific PTE entry function

On VLV we need to flush the TLBs of the Gunit when updating PTEs. We could put this off until we've written a whole block of entries, but we don't currently have a nice place to put that. Signed-off-by: Jesse Barnes --- drivers/char/agp/intel-agp.h |1 + drivers/char/agp/intel-gtt.c | 19

[Intel-gfx] [PATCH 12/25] agp/intel: map more registers for use by the GTT code

We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the register for doing so is above the range we normally map. Map the whole register space to make sure we can get it. Signed-off-by: Jesse Barnes --- drivers/char/agp/intel-gtt.c |2 +- 1 files changed, 1 insertions(+), 1 d

[Intel-gfx] [PATCH 11/25] drm/i915: Enable HDMI on ValleyView

From: Shobhit Kumar HDMI register offsets are different in Valleyview. Add support for the same. Signed-off-by: Beeresh G Signed-off-by: Shobhit Kumar Reviewed-by: Vijay Purushothaman Reviewed-by: Jesse Barnes Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 16 +++

[Intel-gfx] [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions

ValleyView handles force wake differently than previous chipsets, so add a couple of new functions for it. But it's also untested, so no need to call these untested functions yet. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 28 +++- drivers/g

[Intel-gfx] [PATCH 23/25] drm/i915: add ValleyView clock gating init

Set the same bits as IVB plus a few others. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 18 +++ drivers/gpu/drm/i915/intel_display.c | 41 ++ 2 files changed, 59 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH 24/25] drm/i915: add has_turbo bit to driver info struct

Since ValleyView is a gen7 chip but doesn't have the same turbo interface. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c |4 drivers/gpu/drm/i915/i915_drv.h |2 ++ drivers/gpu/drm/i915/intel_display.c |2 +- 3 files changed, 7 insertions(+), 1 deletio

[Intel-gfx] [PATCH 21/25] drm/i915: add HDMI and DP port enumeration on ValleyView

ValleyView is similar to IbexPeak here, but with different register offsets. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 18 ++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 22/25] drm/i915: remove some unneeded debug messages

Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 58accf5..541c0a6 100644 --- a/drivers/gpu/drm/i915/intel_display.c ++

[Intel-gfx] [PATCH 10/25] drm/i915: Enable DP panel power sequencing for ValleyView

From: Shobhit Kumar VLV supports two dp panels, there are two set of panel power sequence registers which needed to be programmed based on the configured pipe. This patch add supports for the same Signed-off-by: Beeresh G Reviewed-by: Vijay Purushothaman Reviewed-by: Jesse Barnes Signed-off-b

[Intel-gfx] [PATCH 07/25] drm/i915: split out DPLL update code from i9xx_crtc_mode_set

ValleyView needs something different here, and it cleans up the function quite a bit. Signed-off-by: Jesse Barnes Signed-off-by: Artem Bityutskiy Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 408 +++-- 1 files changed, 235 insertions(+), 1

[Intel-gfx] [PATCH 09/25] drm/915: program driain latency regs on ValleyView

From: Gajanan Bhat This patch adds support for programming drain latency registers of Pondicherry memory arbiter of Valleyview. Signed-off-by: Gajanan Bhat Reviewed-by: Shobhit Kumar Reviewed-by: Vijay Purushothaman Reviewed-by: Jesse Barnes Signed-off-by: Jesse Barnes --- drivers/gpu/drm/

[Intel-gfx] [PATCH 06/25] drm/i915: add ValleyView registers, stub code, and watermark support

ValleyView is a CedarView-like chip but with an Ivybridge graphics core. This patch adds initial framework for supporting this chip. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 21 + drivers/gpu/drm/i915/i915_drv.h |2 + drivers/gpu/drm/i915/i915_reg

[Intel-gfx] [PATCH 05/25] drm/i915: add DPIO read/write functions for ValleyView

ValleyView and similar hardware (like CedarView) put some display related registers like the PLL controls and dividers on a DPIO bus. Add simple indirect register access routines to get to those registers. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h |4 ++ drivers/g

[Intel-gfx] [RFC] ValleyView support

In this set, you can see why I was asking about register offsets and splitting the display code. Included are a few cleanups to help me keep my sanity, but as I mentioned in my other mail I think we should go further. Many of these are ok to apply as-is, so let me know what order you'd like them

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