On Wed, Oct 19, 2011 at 13:12, Jesse Barnes wrote:
> Latest patches; Eugeni can you reply with your tested-by? I think
> they're all ready for upstream.
>
For the series:
Tested-By: Eugeni Dodonov
Reviewed-By: Eugeni Dodonov
There three reproducible issues I found out, but they were present
On Wed, 19 Oct 2011 08:02:57 -0700, Ben Widawsky wrote:
> On Wed, 19 Oct 2011 12:32:25 +0100
> Chris Wilson wrote:
> > NAK: This failed to detect a hang, leaving my box frozen. I suspect that
> > the value of INSTDONE was fluctuating on the render ring even though we
> > had now requests pending
Transcoder A will always use PLL A and transcoder B will use PLL B. But
transcoder C could use either, so always mask the select bits off before
or'ing in a new value.
Reported-by: Adam Jackson
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 15 ++-
1 files
Just some extra debug output.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2c30e36..c95ac7f 100644
--- a/drivers/gp
The watermark reg for the third pipe is in an unusual offset; add
support for it and set watermarks for 3 pipe configs.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 14 ++
2 files changed, 15 insertions(+), 0
At the point where we check, we can't do much about the failure, but it
can aid debugging. Note that the auto-train override bit will be reset
as part of normal mode setting with this patch if a pipe ever does get
stuck, but that's consistent with the workaround for CPT provided by the
hardware te
Belongs in PCH enable instead. The duplication is worrying and the
specs explicitly list transcoder select *after* actual PLL enable, which
doesn't occur until later.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 25 -
1 files changed, 0 insert
2011/10/19 Adam Jackson :
> On Wed, 2011-10-19 at 18:43 +0400, 4ernov wrote:
>
>> And is it guessed somewhere in case of VBT missing?
>
> Well, not yet, no. Like I said, there's no code at all yet for tweaking
> SDVO LVDS.
OK, it's clear for me now. But is there any right place where I can
hardco
Add two new fields to the intel_crtc struct for 3 pipe support: no_pll
and use_pll_a. The no_pll field is only set on the 3rd pipe to indicate
that it doesn't have a PLL of its own and so shouldn't try to write the
main PLL regs. The use_pll_a field controls which PLL pipe 3 will
share, A or B.
The cursor regs have moved around, add the offsets and new macros for
getting at them.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |8 ++
drivers/gpu/drm/i915/intel_display.c | 40 +
2 files changed, 43 insertions(+), 5 deletions
We can have more than just A and B these days.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 347a949..0e556e7 100644
On IVB with CPT or PPT PCH chips, FDI sync can be done with one or two wires
depending on the board configuration. For 3 pipe configurations, since
FDI B and C share lanes, composite sync must be used. The board design
specs require that composite sync always work in general too, so just
use it b
Add a couple of checks now that we're using the 3rd transcoder:
1) make sure the transcoder PLL enable bit is set for the transcoder
in question
2) when checking actual PLL enable, use the selected PLL number rather
than the transcoder number (they could be different now)
Signed-off-
Well almost anyway. IVB has 3 planes, pipes, transcoders, and FDI
interfaces, but only 2 pipe PLLs. So two of the pipes must use the same
pipe timings (e.g. 2 DP plus one other, or two HDMI with the same mode
and one other, etc.).
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_dma.c
Required for 3 pipe functionality.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_crt.c | 18 +++---
drivers/gpu/drm/i915/intel_hdmi.c | 10 --
2 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm
Add a macro for accessing the two pipe PLLs and add a check to make sure
we don't access a non-existent one in the enable/disable functions.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |6 +++---
drivers/gpu/drm/i915/intel_display.c |6 ++
2 files changed, 9
Just a cleanup to make the mode_set function more manageable.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 45 ++---
1 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i9
Latest patches; Eugeni can you reply with your tested-by? I think
they're all ready for upstream.
Thanks,
Jesse
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On Wed, 19 Oct 2011 12:32:25 +0100
Chris Wilson wrote:
> On Tue, 11 Oct 2011 16:39:09 +0200, Daniel Vetter
> wrote:
> > From: Ben Widawsky
> >
> > This was pulled out of the per ring error handling patch series as it
> > actually fixes two issues, and bikeshedding appears to be going on
> > t
On Wed, 2011-10-19 at 18:43 +0400, 4ernov wrote:
> And is it guessed somewhere in case of VBT missing?
Well, not yet, no. Like I said, there's no code at all yet for tweaking
SDVO LVDS.
> In my case there's
> no OpRegion support (i945GME chipset don't support it as mainboard
> manufacturer info
2011/10/19 Adam Jackson :
> On Wed, 2011-10-19 at 17:48 +0400, 4ernov wrote:
>
>> Thanks, Adam. But is there any pipe setup part specific for certain
>> output? I need to find a place where converter is set to use 24 or 18
>> bit LVDS mode. I examined intel_sdvo.c quite long but still cannot
>> fin
On Wed, 2011-10-19 at 17:48 +0400, 4ernov wrote:
> Thanks, Adam. But is there any pipe setup part specific for certain
> output? I need to find a place where converter is set to use 24 or 18
> bit LVDS mode. I examined intel_sdvo.c quite long but still cannot
> find what I want.
We don't appear t
2011/10/19 Adam Jackson :
> On Wed, 2011-10-19 at 13:08 +0400, 4ernov wrote:
>> Hello,
>>
>> I'm experimenting with i915 kernel module to fix the problem with
>> different brightness of LVDS displays when connected together via
>> Chrontel SDVO converters. My biggest problem is that I simply
>> can
On Wed, 2011-10-19 at 13:08 +0400, 4ernov wrote:
> Hello,
>
> I'm experimenting with i915 kernel module to fix the problem with
> different brightness of LVDS displays when connected together via
> Chrontel SDVO converters. My biggest problem is that I simply
> can't find the place in code where t
On Tue, 11 Oct 2011 16:39:09 +0200, Daniel Vetter
wrote:
> From: Ben Widawsky
>
> This was pulled out of the per ring error handling patch series as it
> actually fixes two issues, and bikeshedding appears to be going on
> there.
>
> First, remove setting hangcheck_count when we do notify ring
Hello,
I'm experimenting with i915 kernel module to fix the problem with
different brightness of LVDS displays when connected together via
Chrontel SDVO converters. My biggest problem is that I simply
can't find the place in code where the mode is set. I seem to find the
place where the device is
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