This problem is covered by various bugs, one of them being:
https://bugzilla.kernel.org/show_bug.cgi?id=37142
At some point there was a "solution" to essentially the same bug (I
believe http://bugzilla.kernel.org/show_bug.cgi?id=13811), but the
problem quickly resurfaced.
There are also similar
This eliminates VGA shimmer on some Ironlake machines which have a
CK505 clock source.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/intel_display.c | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm
The PCH refclk settings are global, so we need to look at all of the
encoders, not just the current encoder when deciding how to configure
it. Also, handle systems with more than one panel (any combination of
PCH/non-PCH eDP and LVDS).
Disable SSC clocks when no panels are connected.
Signed-off-b
I can't find any reference clocks which run at 96MHz as seems to be
indicated from the comments in this code.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/intel_display.c | 14 --
1 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_di
The reference clock configuration must be done before any mode setting
can occur as all outputs must be disabled to change
anything. Initialize the clocks after turning everything off during
the initialization process.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/intel_display.c | 10
These are all KMS related anyways, so don't hide them under other
debug levels.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/intel_bios.c |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios
This includes whether an eDP panel is present, and whether that should
use SSC (and at what frequency)
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/intel_bios.h |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.h
b/drivers/gpu/
Allow SSC to be enabled even when the BIOS disables it for testing SSC paths.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/i915_drv.c |4 ++--
drivers/gpu/drm/i915/intel_display.c |4 +++-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i
This tells the driver whether a CK505 clock source is available on
pre-PCH hardware. If so, it should be used as the non-SSC source,
leaving the internal clock for use as the SSC source.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_bios.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/intel_bios.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 61abef8..4c530fa 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/g
Here's a patch sequence which cleans up a bunch of PCH refclk related
bits. There are a couple of questionable patches that I'd like to see
people look at:
[PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings
[PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time
Here's the mai
On Mon, Sep 26, 2011 at 09:40:12AM -0700, Eric Anholt wrote:
> On Sun, 25 Sep 2011 18:35:31 -0700, Ben Widawsky wrote:
> > Clean the code up, and always use a BO when creating a new buffer. I've
> > not seen any regressions but haven't yet tried this on < Gen6.
> >
> > Cc: Chad Versace
> > Cc: E
On Mon, 26 Sep 2011 19:59:50 +0200
Daniel Vetter wrote:
> Only do it in the hope of resurrecting the gpu. Disable when reset is
> disabled because it seems to tremendously increases our changes to
> actually capture an error_state before the system goes all belly-up.
>
> Signed-off-by: Daniel Ve
On Mon, 26 Sep 2011 13:56:17 -0700, Keith Packard wrote:
> So, what I think we should be doing is using display_clock_mode to
> select between ck505 and internal clock source on pre-PCH hardware. For
> PCH hardware, we unconditionally use the ck505 source for the non-SSC
> reference. When we need
On Mon, 26 Sep 2011 13:38:26 -0700, Kenneth Graunke
wrote:
> On 09/26/2011 01:31 PM, Daniel Vetter wrote:
> > On Mon, Sep 26, 2011 at 11:59:23AM -0700, Kenneth Graunke wrote:
> >> +static int
> >> +gen6_render_ring_flush(struct intel_ring_buffer *ring,
> >> + u32 invalidat
On Fri, 23 Sep 2011 20:07:52 +0100, Chris Wilson
wrote:
> On Fri, 23 Sep 2011 09:15:05 -0700, Keith Packard wrote:
> > What I didn't find there was any mention of the display_clock_mode
> > field; perhaps jbarnes has newer VBIOS sources or actual BDB
> > documentation.
>
> iirc display_clock_mo
On 09/26/2011 01:31 PM, Daniel Vetter wrote:
> On Mon, Sep 26, 2011 at 11:59:23AM -0700, Kenneth Graunke wrote:
>> +static int
>> +gen6_render_ring_flush(struct intel_ring_buffer *ring,
>> + u32 invalidate_domains, u32 flush_domains)
>> +{
>> +u32 flags = 0;
>> +stru
On Mon, Sep 26, 2011 at 11:59:23AM -0700, Kenneth Graunke wrote:
> +static int
> +gen6_render_ring_flush(struct intel_ring_buffer *ring,
> + u32 invalidate_domains, u32 flush_domains)
> +{
> + u32 flags = 0;
> + struct pipe_control *pc = ring->private;
> + u32 sc
On 09/26/2011 12:16 PM, Chris Wilson wrote:
> On Mon, 26 Sep 2011 11:59:23 -0700, Kenneth Graunke
> wrote:
>> From: Jesse Barnes
>
> From the school of "If ain't broke, don't fix it" there needs to be a real
> explanation of why this change is required here.
>
> PIPE_CONTROL and its workaround
On Mon, 26 Sep 2011 20:16:04 +0100, Chris Wilson
wrote:
> PIPE_CONTROL and its workarounds is a very bitter pill to swallow if
> MI_FLUSH continues to function.
If you look at the simulator source code, you'll see that it implements
MI_FLUSH as a specific kind of PIPE_CONTROL. And that MI_FLUSH
On Mon, 26 Sep 2011 21:23:02 +0200, Daniel Vetter wrote:
> On Mon, Sep 26, 2011 at 08:16:04PM +0100, Chris Wilson wrote:
> > On Mon, 26 Sep 2011 11:59:23 -0700, Kenneth Graunke
> > wrote:
> > > From: Jesse Barnes
> >
> > From the school of "If ain't broke, don't fix it" there needs to be a rea
On Mon, Sep 26, 2011 at 08:16:04PM +0100, Chris Wilson wrote:
> On Mon, 26 Sep 2011 11:59:23 -0700, Kenneth Graunke
> wrote:
> > From: Jesse Barnes
>
> From the school of "If ain't broke, don't fix it" there needs to be a real
> explanation of why this change is required here.
>
> PIPE_CONTROL
On Mon, 26 Sep 2011 11:59:23 -0700, Kenneth Graunke
wrote:
> From: Jesse Barnes
>From the school of "If ain't broke, don't fix it" there needs to be a real
explanation of why this change is required here.
PIPE_CONTROL and its workarounds is a very bitter pill to swallow if
MI_FLUSH continues t
On Sep 26, 2011 9:00 PM, "Daniel Vetter" wrote:
>
> Only do it in the hope of resurrecting the gpu. Disable when reset is
> disabled because it seems to tremendously increases our changes to
> actually capture an error_state before the system goes all belly-up.
>
> Signed-off-by: Daniel Vetter
>
Only do it in the hope of resurrecting the gpu. Disable when reset is
disabled because it seems to tremendously increases our changes to
actually capture an error_state before the system goes all belly-up.
Signed-off-by: Daniel Vetter
---
Hi Andrew,
Can you please apply this patch and boot your
From: Jesse Barnes
Signed-off-by: Jesse Barnes
Signed-off-by: Kenneth Graunke
Tested-by: Kenneth Graunke
---
drivers/gpu/drm/i915/i915_reg.h |7 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 131 ---
2 files changed, 124 insertions(+), 14 deletions(-)
On Sun, 25 Sep 2011 18:35:31 -0700, Ben Widawsky wrote:
> Clean the code up, and always use a BO when creating a new buffer. I've
> not seen any regressions but haven't yet tried this on < Gen6.
>
> Cc: Chad Versace
> Cc: Eric Anholt
> Signed-off-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/
Am 22.09.2011 22:35, schrieb Daniel Vetter:
Hi Knut,
The issue has been a bug in libdrm. Can you please update that and retest?
Thanks, Daniel
glxgears / glxinfo are functional again on the i915GM
Thanks,
Knut
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On Sun, Sep 25, 2011 at 04:42:57PM -0700, Ben Widawsky wrote:
> > > static int sandybridge_write_fence_reg(struct drm_i915_gem_object
> > > *obj, diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > b/drivers/gpu/drm/i915/i915_gem_gtt.c index 7a709cd..0c6226b 100644
> > > --- a/drivers/gpu/drm/i
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