[Intel-gfx] [PATCH] drm/i915: Enable GPU reset on Ivybridge.

According to the hardware documentation, GDRST is exactly the same as on Sandybridge. So simply enable the existing code. Signed-off-by: Kenneth Graunke --- drivers/gpu/drm/i915/i915_drv.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) GPU reset does not seem terribly reliable, but

[Intel-gfx] [PATCH] drm/i915: forcewake debugfs fix

Forcewake needs to register itself with drm to use the remove function. The file also should be read only. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_debugfs.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drive

Re: [Intel-gfx] X11 performance regressions

As I do have only a few minutes now, a few comments: 1: The complete trees are compared, all modules/libraries are either old or new. No debug-versions. 2: Speculating about cores is definitely wrong -- the Pentium M Dothan definitely is a single core cpu. 3. There often is a "choked most" (1)

Re: [Intel-gfx] X11 performance regressions

On Wed, 2011-05-11 at 16:46 +0200, Knut Petersen wrote: > Yes, I made some mistakes during my first measurements. > > Below find better results. They are made on the same machine, > with the same kernel, at the same speed, with the same x11perf > program, absolutely nothing changed. You don't men

Re: [Intel-gfx] [PATCH 1/2] drm/i915: add Ivybridge clock gating init function

On Wed, 2011-05-11 at 10:26 -0700, Jesse Barnes wrote: > On Wed, 11 May 2011 13:20:55 -0400 > Adam Jackson wrote: > > Nitpick: Probably either this comment (and its mate in > > gen6_init_clock_gating) should just refer to PCH generically if this is > > going to keep being true, or this instance of

Re: [Intel-gfx] LVDS Undetected

On Wed, 11 May 2011, Travis Allen wrote: > I am now using a nightly build of the driver from last night. > > > > > video=LVDS-1:e > > Unfortunately this didn't enable the LVDS output (at least xrandr > doesn't show it as an available output with a default boot - ie no > xorg customization).

Re: [Intel-gfx] LVDS Undetected

On Wed, 11 May 2011, Oliver Seitz wrote: > > > > video=LVDS-1:e > > > > Unfortunately this didn't enable the LVDS output (at least xrandr doesn't > > show it as an available output with a default boot - ie no xorg > > customization). Does this require an xorg.conf for the output to show up? >

Re: [Intel-gfx] LVDS Undetected

video=LVDS-1:e Unfortunately this didn't enable the LVDS output (at least xrandr doesn't show it as an available output with a default boot - ie no xorg customization). Does this require an xorg.conf for the output to show up? Some months ago I've tried that, I also had no success, with o

Re: [Intel-gfx] LVDS Undetected

I am now using a nightly build of the driver from last night. > > video=LVDS-1:e Unfortunately this didn't enable the LVDS output (at least xrandr doesn't show it as an available output with a default boot - ie no xorg customization). Does this require an xorg.conf for the output to show up?

Re: [Intel-gfx] X11 performance regressions

On Wed, 11 May 2011 16:46:12 +0200, Knut Petersen wrote: > Yes, I made some mistakes during my first measurements. > > Below find better results. They are made on the same machine, > with the same kernel, at the same speed, with the same x11perf > program, absolutely nothing changed. > > I used

[Intel-gfx] [PATCH 9/9] drm/i915: use pipe bpp when setting HDMI bpc

The Intel HDMI encoder can support 8bpc or 12bpc. Set the appropriate value based on the pipe bpp when configuring the output. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_hdmi.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH 6/9] drm/i915: split out Ironlake pipe bpp picking code

Figuring out which pipe bpp to use is a bit painful. It depends on both the encoder and display configuration attached to a pipe. For instance, to drive a 24bpp framebuffer out to an 18bpp panel, we need to use 6bpc on the pipe but also enable dithering. But driving that same framebuffer to a Di

[Intel-gfx] [PATCH 8/9] drm/i915: use pipe bpp in DP link bandwidth calculations

The pipe may be driving various bpp values depending on the display configuration, so take that into account when calculating link bandwidth requirements. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/

[Intel-gfx] [PATCH 5/9] drm/i915: set bpc for DP transcoder

This may not be the default value, so pull the bpc out of the pipe reg and write it to the DP transcoder so proper dithering and signaling occurs. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drive

[Intel-gfx] [PATCH 7/9] drm/i915: split out plane update code

Updating the planes is device specific, so create a new display callback and use it in pipe_set_base. (In fact we could go even further, valid display plane bits have changed with each generation, as has tiled buffer handling.) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH 4/9] drm/i915: don't set transcoder bpc on CougarPoint

This prevents us from setting reserved or incorrect bits on CougarPoint. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 15 +-- 1 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_

[Intel-gfx] [PATCH 1/9] drm: add bit depth parsing

EDID 1.4 digital monitors report the bit depth supported in the input field. Add support for parsing this out and storing the info in the display_info structure for use by drivers. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/drm_edid.c | 55 ++- inc

[Intel-gfx] [PATCH 2/9] drm: parse color format support for digital displays

EDID 1.4 digital displays report the color spaces they support in the features block. Add support for grabbing this data and stuffing it into the display_info struct for driver use. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/drm_edid.c |6 ++ include/drm/drm_crtc.h |5 -

[Intel-gfx] [PATCH 3/9] drm/i915: don't set SDVO color range on ILK+

These bits are reserved on ILK+ (ILK+ provides this feature in the transcoder and pipe configuration instead, which we already set). Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_hdmi.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i

[Intel-gfx] Deep color support and bug fixes

A couple of bug fixes, and some patches to support deep color on Intel chipsets. Thanks, Jesse ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/2] drm/i915: add Ivybridge clock gating init function

On Wed, 11 May 2011 13:20:55 -0400 Adam Jackson wrote: > On Wed, 2011-05-11 at 09:52 -0700, Jesse Barnes wrote: > > > + /* > > +* On Ibex Peak and Cougar Point, we need to disable clock > > +* gating for the panel power sequencer or it will fail to > > +* start up when no ports are

Re: [Intel-gfx] [PATCH 4/7] drm/i915: split out Ironlake pipe bpp picking code

On Tue, 10 May 2011 14:23:18 -0700 Keith Packard wrote: > On Tue, 19 Apr 2011 12:12:38 -0700, Jesse Barnes > wrote: > > Figuring out which pipe bpp to use is a bit painful. It depends on both > > the encoder and display configuration attached to a pipe. For instance, > > to drive a 24bpp fram

Re: [Intel-gfx] [PATCH 1/2] drm/i915: add Ivybridge clock gating init function

On Wed, 2011-05-11 at 09:52 -0700, Jesse Barnes wrote: > + /* > + * On Ibex Peak and Cougar Point, we need to disable clock > + * gating for the panel power sequencer or it will fail to > + * start up when no ports are active. > + */ Nitpick: Probably either this comment (

[Intel-gfx] [PATCH 2/2] drm/i915: split PCH clock gating init

Ibex Peak and CougarPoint already require a different setting (added here), and future chips will likely follow that precedent. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h |1 + drivers/gpu/drm/i915/i915_reg.h |3 ++ drivers/gpu/drm/i915/i915_suspend.c |

[Intel-gfx] [PATCH 1/2] drm/i915: add Ivybridge clock gating init function

Some of the bits have changed, including one we were setting that enables a VGA test mode, preventing pipe B from working at all. So add a new IVB specific function with the right bits. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_dis

Re: [Intel-gfx] LVDS Undetected

On Wed, 11 May 2011, Oliver Seitz wrote: > > > 2) If there is a valid reason for 1, how can I force the output to be > > listed. > > Short answer: You can't. Actually, you already CAN force it on, no patches needed. Adding this to the kernel command line should probably do it: video=LVDS

Re: [Intel-gfx] [PATCH] Remove the memory of Option "AccelMethod"

On 05/10/2011 12:27 PM, Adam Jackson wrote: Signed-off-by: Adam Jackson Reviewed-by: Kenneth Graunke ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] LVDS Undetected

2) If there is a valid reason for 1, how can I force the output to be listed. Short answer: You can't. It is being discussed to implement kernel parameters to force a certain LVDS mode, abd there do exist some patches. But as much as I know there hasn't been a decision made if it e

[Intel-gfx] LVDS Undetected

I am using a D945GSEJT motherboard which has onboard LVDS. Unfortunately whatever I do the LVDS output is not listed in xrandr nor Xorg. It will only list the VGA, DVI, and TV outputs. I have tried using the "nomodeset" option, however that removes *all* outputs from xrandr and only lists a "

Re: [Intel-gfx] X11 performance regressions

Yes, I made some mistakes during my first measurements. Below find better results. They are made on the same machine, with the same kernel, at the same speed, with the same x11perf program, absolutely nothing changed. I used x11perfcomp -ro and sorted the output, worst results for the currrent gi