On Sat, Apr 16, 2011 at 08:05:42AM +0100, Chris Wilson wrote:
> On Thu, 14 Apr 2011 21:56:02 +0200, Paul Menzel
> wrote:
> But Ben... I seemed to have missed the real reason why we need the
> spinlock. You have to remind me or else I will keep whining on like a
> broken record. ;-)
> -Chris
>
The 965G (Broadwater) and 965GM (Crestline) chipsets had many errata in
handling pages allocation above 4GiB. So we should be careful never to
allocate and attempt to pass such through to the GPU and so limit
ourselves to GFP_DMA32 on those chipsets.
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Knut Petersen reported a GPU hang when he left x11perf running
overnight. The error state quite clearly indicates that plane A was
enabled without being fully setup:
PGTBL_ER: 0x0010
Display A: Invalid GTT PTE
Plane [0]:
CNTR: c100
STRIDE: 0c80
SIZE: 03ff04ff
POS:
From: Zhao Yakui
... otherwise the TV type will be misdetected and cause spurious
connections.
This was originally applied as fb8b5a39b6310379d7b54c0c7113703a8eaf4a57
(drm/i915: Configure the TV sense state correctly on GM45 to make TV
detection reliable)
Eric: Shortly after applying this patch
