Nice. The consensus is that this ioctl is required, just a few comments
inline.
On Thu, 31 Mar 2011 18:31:49 -0700, Ben Widawsky wrote:
> With the invention of forcewake (DevGT) , userspace tools to diagnose
> problems are no longer reliable. This will provide userspace a mechanism
> to read regi
Dear Sir,
I have a HID device.
How can I grab the data from keyboard queue, and remove it from queue?
Thanks & Best Regards.
Vincent Chien 簡郁峰
UG / S&C BU / POS PLM / RDII / SW
環鴻科技股份有限公司
Tel : 886-2-27820366 Ext : 3112
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A
With the invention of forcewake (DevGT) , userspace tools to diagnose
problems are no longer reliable. This will provide userspace a mechanism
to read registers through an IOCTL, as well as root permission to write
to registers.
The code tries to be smart about which registers can be read and
writ
With the invention of forcewake (DevGT) , userspace tools to diagnose
problems are no longer reliable. This will provide userspace a mechanism
to read registers through an IOCTL, as well as root permission to write
to registers.
The code tries to be smart about which registers can be read and
writ
On Thu, 31 Mar 2011 08:29:31 +0100, Chris Wilson
wrote:
> On Wed, 30 Mar 2011 14:45:11 -0700, Eric Anholt wrote:
> > On Wed, 30 Mar 2011 18:16:11 +0100, Chris Wilson
> > wrote:
> > > On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt wrote:
> > > > And what about a CPU write through the GTT?
> >
On Wed, 30 Mar 2011 13:01:10 -0700
Eric Anholt wrote:
> They're used in one place, and not providing any descriptive value,
> with their names just being approximately the conjunction of the
> struct name and the struct field.
>
> This diff was produced with gcc -E, copying the new struct defini
On Wed, 30 Mar 2011 13:01:09 -0700
Eric Anholt wrote:
> We used to have these from the product of (pch, non-pch) * (pipe a,
> pipe b). Now we can just use the nice per-pipe reg macros in the
> split out crtc_mode_sets.
>
> Signed-off-by: Eric Anholt
> ---
Reviewed-by: Jesse Barnes
--
Jesse
On Wed, 30 Mar 2011 13:01:08 -0700
Eric Anholt wrote:
> Signed-off-by: Eric Anholt
> ---
> drivers/gpu/drm/i915/intel_display.c | 119 ++---
> 1 files changed, 36 insertions(+), 83 deletions(-)
Reviewed-by: Jesse Barnes
--
Jesse Barnes, Intel Open Source Technol
On Wed, 30 Mar 2011 13:01:07 -0700
Eric Anholt wrote:
> Ironlake is where the PCH split started.
>
> Signed-off-by: Eric Anholt
> ---
> drivers/gpu/drm/i915/intel_display.c | 361
> ++
> 1 files changed, 150 insertions(+), 211 deletions(-)
>
Reviewed-by: Jes
- Original message -
> On Thu, 31 Mar 2011 16:16:27 +0100, Steven Newbury
> wrote:
> > - Original message -
> > > On Wed, 30 Mar 2011 17:07:11 +0100
> > > Chris Wilson wrote:
> > >
> > > > Once a NAK has been asserted by the slave, we need to reset the
> > > > GMBUS controller in
On Thu, 31 Mar 2011 16:16:27 +0100, Steven Newbury
wrote:
> - Original message -
> > On Wed, 30 Mar 2011 17:07:11 +0100
> > Chris Wilson wrote:
> >
> > > Once a NAK has been asserted by the slave, we need to reset the GMBUS
> > > controller in order to continue. This is done by assertin
- Original message -
> On Wed, 30 Mar 2011 17:07:11 +0100
> Chris Wilson wrote:
>
> > Once a NAK has been asserted by the slave, we need to reset the GMBUS
> > controller in order to continue. This is done by asserting the Software
> > Clear Interrupt bit and then clearing it again to res
Dear All.
I have Opensuse 11.1 and the output of fbset -i gives me:
mode "1024x768-76"
# D: 78.653 MHz, H: 59.949 kHz, V: 75.694 Hz
geometry 1024 768 1024 768 32
timings 12714 128 32 16 4 128 4
rgba 8/16,8/8,8/0,8/24
endmode
Frame buffer device information:
Name: VESA
Dear All,
After recent update of:
kernel-2.6.38.2-9.fc15
xorg-x11-server-1.10.0-7.fc15
mesa-7.11-0.3.20110330.0.fc15
glxgears output window shows no gears, just black background.
Video chipset:
00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML
Express Graphics Controll
On Wed, 30 Mar 2011 13:01:07 -0700, Eric Anholt wrote:
> Ironlake is where the PCH split started.
Jesse, what's your objection here? IOW, where's your reviewed-by ;-)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing li
On Wed, 30 Mar 2011 13:01:01 -0700, Eric Anholt wrote:
> In doing new chipset enablement for the first time in quite a while,
> it sunk in just how bad the spaghetti in our modeset path was these
> days. I think that splitting the crtc_mode_set up a bit gets us a
> more readable path for whicheve
On Wed, 30 Mar 2011 14:45:11 -0700, Eric Anholt wrote:
> On Wed, 30 Mar 2011 18:16:11 +0100, Chris Wilson
> wrote:
> > On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt wrote:
> > > And what about a CPU write through the GTT?
> >
> > Even on SNB these are still UC. And we should try hard not to,
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