Re: [Intel-gfx] Operation ordering?

2010-11-02 Thread Peter Clifton
On Tue, 2010-11-02 at 21:31 +, Peter Clifton wrote: > Running with debug options set to always flush after each primitive > fixes the issue, as does a judicial insertion of glFlush into my > rendering code after changing the stencil test state, but before drawing > more geometry. Please ignore

[Intel-gfx] Operation ordering?

2010-11-02 Thread Peter Clifton
I'm unfamiliar with how this works, so please bear with me. I'm attempting to track down an intermittent rendering bug in my application which appears to be related to stencil information not being correct at the time primitives are rendered. The rendering builds up by rendering into the stencil b

Re: [Intel-gfx] [PATCH 4/4] cpuidle: Hack iowait weighting to avoid C-state reduction for graphics.

2010-11-02 Thread Chris Wilson
On Tue, 02 Nov 2010 21:00:31 +0100, Alexey Fisher wrote: > If this patches about perforamnce issue on 9450gm and sleep state on > CPU, than it do not work for me. > > I applied your patches on the top of 3e7b033 (drm/i915: Use the agp_size > determined from the GTT), the 3/4 was rejected so id i

Re: [Intel-gfx] [PATCH 4/4] cpuidle: Hack iowait weighting to avoid C-state reduction for graphics.

2010-11-02 Thread Alexey Fisher
Am Dienstag, den 02.11.2010, 08:42 -0700 schrieb Eric Anholt: > On Tue, 02 Nov 2010 20:20:14 +0800, ykzhao wrote: > > On Tue, 2010-11-02 at 04:23 +0800, Eric Anholt wrote: > > > Improves nexuiz performance by about 1% on my system. > > > > CC: Arjan and linux-acpi mailing list. > > > > It seems

Re: [Intel-gfx] [PATCH 4/4] cpuidle: Hack iowait weighting to avoid C-state reduction for graphics.

2010-11-02 Thread Eric Anholt
On Tue, 02 Nov 2010 20:20:14 +0800, ykzhao wrote: > On Tue, 2010-11-02 at 04:23 +0800, Eric Anholt wrote: > > Improves nexuiz performance by about 1% on my system. > > CC: Arjan and linux-acpi mailing list. > > It seems that the selection of C-state will become very sensitive to IO > wait after

Re: [Intel-gfx] intel_prepare_render(intel); unhelpful?

2010-11-02 Thread Eric Anholt
On Mon, 01 Nov 2010 22:19:34 +, Peter Clifton wrote: > On Mon, 2010-11-01 at 14:41 -0700, Eric Anholt wrote: > > > I'm going to look at the case I "think" I hit an improvement for and > > > dissect _why_, then get back to you. > > I'll check this again shortly.. (I recall I was testing this w

Re: [Intel-gfx] [PATCH] drm/i915: Add aub debug support for kernel

2010-11-02 Thread Liu Aleaxander
Hi Chris, On Tue, Nov 2, 2010 at 6:02 PM, Chris Wilson wrote: > On Tue,  2 Nov 2010 17:11:36 +0800, Yuanhan Liu wrote: >> The AUB file is a file format used by Intel's internal simulation >> and other validation tools. The content of an aub file is a subset >> collection of all the data needed b

Re: [Intel-gfx] [PATCH 4/4] cpuidle: Hack iowait weighting to avoid C-state reduction for graphics.

2010-11-02 Thread ykzhao
On Tue, 2010-11-02 at 04:23 +0800, Eric Anholt wrote: > Improves nexuiz performance by about 1% on my system. CC: Arjan and linux-acpi mailing list. It seems that the selection of C-state will become very sensitive to IO wait after the multi factor is changed from 10 to 1000. Maybe only one IO/wa

Re: [Intel-gfx] [regression] drm/i915: Eliminate nested get/put pages

2010-11-02 Thread Chris Wilson
On Tue, 02 Nov 2010 13:01:10 +0100, Alexey Fisher wrote: > this is regression seems to depend on xserver-xorg-video-intel version. > > xserver-xorg-video-intel version 2:2.12.0-1ubuntu5 > i used till kernel 2.6.36-07547-g100519e, which was fine. > > no i use xserver-xorg-video-intel > 2:2.12.90

[Intel-gfx] [regression] drm/i915: Eliminate nested get/put pages

2010-11-02 Thread Alexey Fisher
this is regression seems to depend on xserver-xorg-video-intel version. xserver-xorg-video-intel version 2:2.12.0-1ubuntu5 i used till kernel 2.6.36-07547-g100519e, which was fine. no i use xserver-xorg-video-intel 2:2.12.902+git20101028.b066ddda-0ubuntu0sarvatt2~maverick what make kernel oops on

Re: [Intel-gfx] [PATCH] drm/i915: SNB BLT workaround

2010-11-02 Thread Chris Wilson
On Tue, 2 Nov 2010 17:08:09 +0800, "Zou, Nanhai" wrote: > >>-Original Message- > >>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > >>Sent: 2010年11月2日 17:05 > >>To: Zou, Nanhai; intel-gfx@lists.freedesktop.org > >>Cc: Zou, Nanhai > >>Subject: Re: [PATCH] drm/i915: SNB BLT worka

Re: [Intel-gfx] Fwd: 2.6.36-rc5 i915 regression

2010-11-02 Thread Seblu
This seems to be fixed in 2.6.37-rc1 and lastest git tree. :) Thanks guys! On Tue, Oct 26, 2010 at 10:49 AM, Seblu wrote: > On Tue, Oct 26, 2010 at 10:30 AM, Chris Wilson > wrote: >> On Tue, 26 Oct 2010 01:19:50 +0200, Seblu wrote: >>> Hello Chris, >>> >>> i've tryed last git kernel with edp-

Re: [Intel-gfx] [PATCH] drm/i915: Add aub debug support for kernel

2010-11-02 Thread Chris Wilson
On Tue, 2 Nov 2010 17:11:36 +0800, Yuanhan Liu wrote: > The AUB file is a file format used by Intel's internal simulation > and other validation tools. The content of an aub file is a subset > collection of all the data needed by GPU. > > Here now just collects the data that are going to be writ

Re: [Intel-gfx] [PATCH 2/2] agp/intel: restore cache behavior on sandybridge

2010-11-02 Thread Chris Wilson
Applied both to -next, thanks. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Fix the graphics frequency clamping at init and when IPS is active.

2010-11-02 Thread Chris Wilson
On Mon, 1 Nov 2010 14:12:01 -0700, Eric Anholt wrote: > From: Jesse Barnes > > Part of the issue here was that Eric slipped in a debug hack for > testing the i915 IPS code before the intel_ips.c driver had landed. > This caused the driver to always use the full range of frequencies, > which is

[Intel-gfx] [PATCH 2/2] agp/intel: restore cache behavior on sandybridge

2010-11-02 Thread Zhenyu Wang
This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original

[Intel-gfx] [PATCH 1/2] agp/intel: fix cache control for sandybridge

2010-11-02 Thread Zhenyu Wang
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang --- drivers/char/agp/intel-gtt.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/ag

[Intel-gfx] [PATCH] drm/i915: Add aub debug support for kernel

2010-11-02 Thread Yuanhan Liu
The AUB file is a file format used by Intel's internal simulation and other validation tools. The content of an aub file is a subset collection of all the data needed by GPU. Here now just collects the data that are going to be written into register, since the others data like ring buffer, buffer

Re: [Intel-gfx] [PATCH] drm/i915: SNB BLT workaround

2010-11-02 Thread Zou, Nanhai
>>-Original Message- >>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] >>Sent: 2010年11月2日 17:05 >>To: Zou, Nanhai; intel-gfx@lists.freedesktop.org >>Cc: Zou, Nanhai >>Subject: Re: [PATCH] drm/i915: SNB BLT workaround >> >>On Tue, 2 Nov 2010 16:31:01 +0800, Zou Nan hai wrote: >>>

Re: [Intel-gfx] [PATCH] drm/i915: SNB BLT workaround

2010-11-02 Thread Chris Wilson
On Tue, 2 Nov 2010 16:31:01 +0800, Zou Nan hai wrote: > on some stepping of SNB cpu, the first command to be parsed in BLT > command streamer should be MI_BATCHBUFFER_START > otherwise the GPU may hang. Then just add the workaround to the init routine. -Chris -- Chris Wilson,

[Intel-gfx] [PATCH] drm/i915: SNB BLT workaround

2010-11-02 Thread Zou Nan hai
on some stepping of SNB cpu, the first command to be parsed in BLT command streamer should be MI_BATCHBUFFER_START otherwise the GPU may hang. Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/intel_ringbuffer.c | 89 +- 1 files changed, 86