[Intel-gfx] Row0 EU0 never present in intel_gpu_top output

Just a final observation.. having graphed the EU idle data from my bastardised intel_gpu_top application. Row0 EU0 never shows up as being used. Nor does it ever seem to appear in my intel_gpu_top profiles. Can anyone else confirm this on a GM45 or other G4X generation chip? I'm wondering if it i

Re: [Intel-gfx] Speed boost disabling RCC clock gating ECO

On Sat, 2010-10-30 at 03:34 +0100, Peter Clifton wrote: > sudo intel_reg_write 0x21D0 0x1000207 > Value before: 0x307 > Value after: 0x207 > > > This boosted FPS of my displaylist frame benchmark from 35fps to 37fps. > > This was clearing bit 8 of ECOSKPD, which is controlling the following > E

[Intel-gfx] Speed boost disabling RCC clock gating ECO

Hi guys, Just a note on a data-point I found here: sudo intel_reg_read 0x21D0 [sudo] password for pcjc2: 0x21D0 : 0x307 sudo intel_reg_write 0x21D0 0x1000207 Value before: 0x307 Value after: 0x207 This boosted FPS of my displaylist frame benchmark from 35fps to 37fps. This was clearing bit 8

Re: [Intel-gfx] Another GPU profile (with better CPU code)

On Sat, 2010-10-30 at 01:54 +0100, Peter Clifton wrote: DOH! -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone,

[Intel-gfx] Another GPU profile (with better CPU code)

This one is clearer, as I used a huge displaylist to keep the GPU busy. It is the same frame as in the previous graphs, just in a displaylist. There are still some obvious stalls which aren't easy to explain. I've highlighted them in red, but note that there are two different "classes" of stall, s

Re: [Intel-gfx] High-resolution intel_gpu_top output

On Sat, 2010-10-30 at 00:08 +0100, Peter Clifton wrote: > It is pretty hard to make out, but I _think_ I'm seeing the GPU starved > at certain points. It looks like the URB busy flag at 100% for these > portions of the profile. I've highlighted them in RED as the bad stalls > I'm worried about. I

Re: [Intel-gfx] [PATCH] enable BLT acceleate on gen6

On Fri, 29 Oct 2010 13:18:32 +0800, Zou Nan hai wrote: > uxa: enable BLT command on gen6, > BLT command will goto BLT ring buffer > on gen6. Just spotted one little fix required, and a couple of other suggestions (as before). Splitting it up into 3 little patches would be best. > S

[Intel-gfx] High-resolution intel_gpu_top output

Hi guys, Would a utility to produce views such as the attached help debug performance bottlenecks? I took intel_gpu_top, ripped out all the bargraph and sorting code, then taught it to spit out a CSV file. For the graph below, I took data for a fraction of a second, sampling with no delays (just

Re: [Intel-gfx] [PATCH] drm/i915: Fix KMS regression on Sandybridge/CPT

On Fri, 29 Oct 2010 10:34:51 +0800, Zhenyu Wang wrote: > On 2010.10.28 10:50:04 +0100, Chris Wilson wrote: > > I've shrunk the patch to just the FDI portion, pushed to staging for > > review. > > Current drm-intel-staging still fails unfortunately.. I'm very interested to know which was the mag

Re: [Intel-gfx] [PATCH] enable BLT acceleate on gen6

On Fri, 29 Oct 2010 13:18:32 +0800, Zou Nan hai wrote: > uxa: enable BLT command on gen6, > BLT command will goto BLT ring buffer > on gen6. Can we break this down into two patches? 1. enable BLT batches. 2. re-enable snb 2d. [3. renaming i830_uxa] > +#define RENDER_BATCH

Re: [Intel-gfx] Small graphics corruption in QT apps, tiling corruption / hang in flash

On Fri, 29 Oct 2010 03:49:06 +0100, Peter Clifton wrote: > Hi guys, > > Just a heads-up here. I don't use many QT apps, so I don't know when > this first started occurring, but with "late" drivers, (all known drm > kernel fixes merged), I noticed the following corruptions. I'm not sure > who's bu

Re: [Intel-gfx] [PATH v2 6/6] Xv: dont call intel_wait_for_scanline on Sandybridge

On Thu, 28 Oct 2010 23:42:05 -0700, Kenneth Graunke wrote: > On Tuesday 26 October 2010 19:17:33 Xiang, Haihao wrote: > > MI_LOAD_SCAN_LINE_INCL command is not available on sandybridge. > > > > Signed-off-by: Xiang, Haihao > > --- > > src/intel_video.c |2 +- > > 1 files changed, 1 inserti