[Intel-gfx] [PATCH] enable blt acceleration on gen6

uxa: enable blt acceleration on gen6 hardware. Signed-off-by: Zou Nan hai --- src/i830_reg.h |2 + src/intel.h |4 ++ src/intel_batchbuffer.c | 37 +--- src/intel_batchbuffer.h | 10 ++- src/intel_driver.c |2 - src/intel_uxa.c

[Intel-gfx] [PATH v2 6/6] Xv: don't call intel_wait_for_scanline on Sandybridge

MI_LOAD_SCAN_LINE_INCL command is not available on sandybridge. Signed-off-by: Xiang, Haihao --- src/intel_video.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/intel_video.c b/src/intel_video.c index afc2405..cdff149 100644 --- a/src/intel_video.c +++ b/src/intel

[Intel-gfx] [PATH v2 5/6] Xv: enable TextureAdaptor for Sandybridge

Signed-off-by: Xiang, Haihao --- src/intel_video.c |8 ++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/intel_video.c b/src/intel_video.c index 5d16778..afc2405 100644 --- a/src/intel_video.c +++ b/src/intel_video.c @@ -364,7 +364,6 @@ void I830InitVideo(ScreenPtr s

[Intel-gfx] [PATH v2 4/6] Xv: setup pipeline for Xv on Sandybridge

Signed-off-by: Xiang, Haihao --- src/brw_structs.h | 100 src/i965_reg.h | 98 src/i965_video.c| 627 +++ src/intel.h |4 + src/intel_batchbuffer.c | 25 ++- src/intel_video.h |7 +

[Intel-gfx] [PATH v2 3/6] Xv: fragments for xv on Sandybridge.

Need to update intel-gen4asm to build these fragments Signed--off-by: Xiang, Haihao --- configure.ac|2 +- src/render_program/Makefile.am | 27 +++- src/render_program/exa_wm_src_affine.g6a| 47 + src/render_pro

[Intel-gfx] [PATH v2 2/6] Xv: Send instruction doesn't use implied move when sampling YUV surface

The two fragments will be reused for sampling YUV surface and send doesn't have implied move on Sandybridge Signed-off-by: Xiang, Haihao --- src/render_program/exa_wm_src_sample_argb.g4a |3 ++- src/render_program/exa_wm_src_sample_argb.g4b |3 ++- src/render_program/exa_wm_src

[Intel-gfx] [PATH v2 1/6] Xv: set the surface state base address

To prepare for Xv on Sandybridge. It is easy to fill the binding table without relocation and make sure that the pointer to binding table only uses bits[15:0]. Signed-off-by: Xiang, Haihao --- src/i965_video.c | 141 + 1 files changed, 67 inse

[Intel-gfx] [PATH v2 0/6] Xv on Sandybridge

Here is the set of patches to enable texture adaptor on Sandybridge. Currently you need to turn off shadow in /etc/xorg.conf to use texture video on Sandybridge v2: refresh the patches, fix a conflict with a recent commit on master ___ Intel-gfx mailing

Re: [Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT engine

>>-Original Message- >>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] >>Sent: 2010年10月26日 17:13 >>To: Zou, Nanhai; intel-gfx@lists.freedesktop.org >>Subject: RE: [Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT >>engine >> >>On Tue, 26 Oct 2010 16:23:24 +0800, "Zou, Na

Re: [Intel-gfx] FPS performance increase when deliberately spinning the CPU with an unrelated task

On Mon, 2010-10-25 at 13:14 -0700, Eric Anholt wrote: I'm taking a bet on memory bandwidth being the constraint for fill limited applications. glxgears manages 59fps at full screen (minus title bar), which is 1680x1024, giving a pixel rate of approx 100Mpix/second (Ignoring over-fill) Assuming 2

Re: [Intel-gfx] intel graphics performance thought

On Tue, 26 Oct 2010 04:35:33 +0100, Peter Clifton wrote: > On Mon, 2010-10-25 at 12:44 -0700, Eric Anholt wrote: > > > So, what if the problem is that our URB allocations aren't big enough? > > I would expect that to look kind of like what I'm seeing. One > > experiment would be to go double the

Re: [Intel-gfx] Fwd: 2.6.36-rc5 i915 regression

On Tue, 26 Oct 2010 10:49:01 +0200, Seblu wrote: > On Tue, Oct 26, 2010 at 10:30 AM, Chris Wilson > wrote: > > Depending on where the tip was, at least one suspend regression was > > recently fixed. It would be useful to recheck with 64193406. > Yes i have this patch in, and the issue is still h

Re: [Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT engine

On Tue, 26 Oct 2010 16:23:24 +0800, "Zou, Nanhai" wrote: > I do not quite understand your point. > How can we mix blitter command with render command in a batch buffer? We can't. We also can't mix render targets/sources between concurrent batch buffers either, at the moment. (I'd much rathe

Re: [Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT engine

>>-Original Message- >>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] >>Sent: 2010年10月26日 16:38 >>To: Zou, Nanhai; Zou, Nanhai; intel-gfx@lists.freedesktop.org >>Subject: RE: [Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT >>engine >> >>On Tue, 26 Oct 2010 16:31:47 +0

Re: [Intel-gfx] Fwd: 2.6.36-rc5 i915 regression

On Tue, Oct 26, 2010 at 10:30 AM, Chris Wilson wrote: > On Tue, 26 Oct 2010 01:19:50 +0200, Seblu wrote: >> Hello Chris, >> >> i've tryed last git kernel with edp-fixes from >> git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/drm-intel.git, >> i've the following result : >> http://videobin.o

Re: [Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT engine

On Tue, 26 Oct 2010 16:31:47 +0800, "Zou, Nanhai" wrote: > Even if we can implement the batch buffer in a modal way. > I think it is not the best usage model. > Render engine and BLT engine are separate engines on gen6+. > For them to run one by one will not maximum the GPU usage. What usage patt

Re: [Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT engine

>>-Original Message- >>From: intel-gfx-bounces+nanhai.zou=intel@lists.freedesktop.org >>[mailto:intel-gfx-bounces+nanhai.zou=intel@lists.freedesktop.org] On >>Behalf Of Zou, Nanhai >>Sent: 2010年10月26日 16:23 >>To: Chris Wilson; intel-gfx@lists.freedesktop.org >>Subject: Re: [Intel-gf

[Intel-gfx] Rotating the screen 180 degrees

Hello I am using the AMPRO ETX 802 board. It comes with Intel 855GME chipset (82855GME + 82801DBM). On top of that hardware I have the INTEGRITY OS. Its BSP has a generic PCI VGA driver. What I need is to rotate the screen 180 degrees. The basic drives supported by INTEGRITY does not has

Re: [Intel-gfx] Fwd: 2.6.36-rc5 i915 regression

On Tue, 26 Oct 2010 01:19:50 +0200, Seblu wrote: > Hello Chris, > > i've tryed last git kernel with edp-fixes from > git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/drm-intel.git, > i've the following result : > http://videobin.org/+2a3/2kn.ogg > > with intel-drm-next from > git://git.kern

Re: [Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT engine

>>-Original Message- >>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] >>Sent: 2010年10月26日 16:18 >>To: Zou, Nanhai; intel-gfx@lists.freedesktop.org >>Subject: Re: [Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT >>engine >> >>On Tue, 26 Oct 2010 15:33:15 +0800, Zou Nan

Re: [Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT engine

On Tue, 26 Oct 2010 15:33:15 +0800, Zou Nan hai wrote: > intel: on gen6, BLT commands stay in a seperate BLT ring > buffer. Split render engine batch and BLT engine batch > on gen6. No. The batch buffer needs to be modal, and upon a context switch flushes the current batch. Otherw

[Intel-gfx] [PATCH 2/2] use BLT command to accelerate uxa on gen6.

uxa: enable accelerate for uxa_copy and uxa_solid on gen6. Signed-off-by: Zou Nan hai --- src/i830_reg.h |2 + src/intel_batchbuffer.c | 35 ++-- src/intel_batchbuffer.h | 31 ++- src/intel_driver.c |3 +- src/intel_uxa.c | 230

[Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT engine

intel: on gen6, BLT commands stay in a seperate BLT ring buffer. Split render engine batch and BLT engine batch on gen6. Signed-off-by: Zou Nan hai --- src/i830_3d.c |2 +- src/i830_render.c | 16 +++-- src/i915_3d.c |2 +- src/i915_3d.h

Re: [Intel-gfx] [PATCH] drm/i915: set scan-buffer as uncached on Sandybridge

On Mon, Oct 25, 2010 at 11:42 AM, Zhenyu Wang wrote: > Display engine on Sandybridge is not coherent with LLC, so > try to always bind display buffer as uncached on Sandybridge. > This fixed screen artifacts seen by using blit engine on Sandybridge. Also I assume you need to set this back to the