Make sure hotplug is enabled, or the hotplug interrupt will not be
invoked. And, for sandybridge, the bit definition for hotplug on
SDE is changed. So, update the code to new definition.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30378
Cc: sta...@kernel.org
Signed-off-by: Yuanhan Liu
On my 965 on unload of driver.
[ cut here ]
WARNING: at /home/airlied/kernel/linux-2.6/lib/dma-debug.c:686
dma_debug_device_change+0x11f/0x19d()
Hardware name: HP Compaq 2510p Notebook PC
pci :00:02.0: DMA-API: device driver has pending DMA allocations
while released fr
The time between start of the pixel clock and backlight enable is a basic
panel timing constraint. If the Panel Power On/Off registers are found
to be 0, assume we are booting without VBIOS initialization and set these
registers to something reasonable.
Change-Id: Ibed6cc10d46bf52fd92e0beb25ae352
I don't think 0 is a reasonable value for any of those fields, so
checking them against 0 should be fine.
Jesse
On Thu, 7 Oct 2010 16:48:51 -0700
Bryan Freed wrote:
> My change tries to detect the lack of initialization by A) finding no VBT,
> and B) finding 0 values in these registers.
>
> Bu
My change tries to detect the lack of initialization by A) finding no VBT,
and B) finding 0 values in these registers.
But what if there is a VBIOS out there that really wants these values to be
0? I provide for that case by checking for VBT.
Is this a reasonable case? If not, I have no problem
We can skip most of the link training step if we use the VBT provided
values.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 146 ---
1 files changed, 89 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers
Cache the first 4 bytes of DPCD data in the eDP case. It's unlikely to
change and can save us some trouble at link training time.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 20
2 files changed, 21 insertions
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 19e0d65..8e019c8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm
We don't use the CPU DP PLL with PCH attached eDP panels, so don't
bother to enable it.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
inde
Needed on Ibex Peak and Cougar Point or the panel won't always come on.
Cc: sta...@kernel.org
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |3 +++
drivers/gpu/drm/i915/intel_display.c |7 +++
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/driv
On Sat, Oct 2, 2010 at 11:07 AM, Zhenyu Wang wrote:
> On 2010.10.01 22:27:45 +0200, Seblu wrote:
>> On Fri, Oct 1, 2010 at 3:22 PM, Chris Wilson
>> wrote:
>> > On Fri, 1 Oct 2010 12:55:56 + (UTC), Seblu wrote:
>> >> I've the same kind trouble with -rc6 and my dell e6410. When module i915
>
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c |8
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a72335e..5a22887 100644
--- a
Wait for vblank after enabling a pipe, make the error messages more
informative, and wait for the pipe to turn off when we disable it.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/
CPU eDP needs a different reference clock than PCH eDP, which uses the
standard PCH refclk of 120MHz.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gp
As with other PCH DP connections.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5fee124..6135875 100644
--- a/driver
We do this later (and more properly) when we enable FDI, so we don't
need to do it here.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 21 -
1 files changed, 0 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/driv
Enable SSC on PCH eDP if possible.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 19 +++
1 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9614747..2d0c893
On Thu, 07 Oct 2010 23:55:38 +0100
Chris Wilson wrote:
> On Thu, 7 Oct 2010 15:48:14 -0700, Bryan Freed wrote:
> > The time between start of the pixel clock and backlight enable is a basic
> > panel timing constraint. If no VBIOS Table is found, and the Panel Power
> > On/Off registers are foun
We need to use some of these values in eDP configurations, so be sure to
fetch them and store them in the i915 private structure.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 18 +-
drivers/gpu/drm/i915/intel_bios.c | 60 ++---
i
The _DSM method on the integrated graphics device can tell us which
connectors are muxable, so add support for making the call and parsing
out the connector info.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/Makefile|2 +
drivers/gpu/drm/i915/i915_dma.c |2 +
drivers
Enable the panel before adjusting eDP link params, make sure the panel
is idle after powering it on before proceeding with other activity,
delay backlight enable to avoid visible flicker.
Also avoid using VDD per hw team recommendation; it can conflict with
the builtin panel power sequencing logic
FDI training needs to done and idle for PCH eDP and before we turn the
pipes on, and various eDP checks need to account for PCH attached eDP.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 67 --
1 files changed, 32 insertions(+), 35 dele
Since we set the output type of PCH attached eDP panels to
INTEL_OUTPUT_eDP this function would never return true when it should.
It's been replaced by working functions.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |5 ++---
drivers/gpu/drm/i915/intel_dp.c | 1
The display code needs to distinguish between CPU and PCH attached eDP
panels, so add some helpers to handle that.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 19 +++
drivers/gpu/drm/i915/intel_drv.h |1 +
2 files changed, 20 insertions(+), 0 deletion
Most of the PCH eDP checks are redundant, so document the functions in
preparation for removing most of the calls.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 92 ---
1 files changed, 57 insertions(+), 35 deletions(-)
diff --git a/driv
With the old check we'd never set lane_count or bpp to different values
on PCH attached eDP panels.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915
If is_edp is true, is_pch_edp will always be true. So limit the calls
to the latter function to places where the distinction actually matters.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 36
1 files changed, 16 insertions(+), 20 delet
Here's the set of PCH eDP fixes I came up with once I received my Sony
Vaio. I found a few, non-PCH issues in the process, and took the
opportunity to enhance our eDP support to avoid most of the DP training
if the VBIOS gives us good data.
This patchset is against ickle's drm-intel-next branch a
On Thu, 7 Oct 2010 15:48:14 -0700, Bryan Freed wrote:
> The time between start of the pixel clock and backlight enable is a basic
> panel timing constraint. If no VBIOS Table is found, and the Panel Power
> On/Off registers are found to be 0, assume we are booting without VBIOS
> initialization a
The time between start of the pixel clock and backlight enable is a basic
panel timing constraint. If no VBIOS Table is found, and the Panel Power
On/Off registers are found to be 0, assume we are booting without VBIOS
initialization and set these registers to something reasonable.
TEST=Repeat th
On Wed, Oct 06, 2010 at 10:54:53AM -0400, Andrew Lutomirski wrote:
> On Wed, Oct 6, 2010 at 10:50 AM, Rasto Sramek wrote:
> >> AFAICT Zaphod mode is one device but multiple X servers (presumably
> >> used independently by different people). I think very few drivers
> >> support it these days.
> >
On Thu, 2010-10-07 at 12:41 +0100, Peter Clifton wrote:
> On Wed, 2010-10-06 at 15:27 -0700, Eric Anholt wrote:
>
> > Of this, I'd say that you're spending a surprising amount of time in
> > texture fetch. Finding ways to reduce texture bandwidth may pay off,
> > assuming that (texture fetch / sa
Dmitry Nezhevenko inhex.net> writes:
>
>
> Hi.
>
> I've finally tried to use VA API on my GM45-based laptop and got followed:
Exactly the same situation as yours here. Laptop: Acer extensa 5635, GM45
chipset (Intel X4500MHD).
What I did:
- freshly installed Ubuntu 10.10rc
- got the latest
On Wed, 2010-10-06 at 15:27 -0700, Eric Anholt wrote:
> Of this, I'd say that you're spending a surprising amount of time in
> texture fetch. Finding ways to reduce texture bandwidth may pay off,
> assuming that (texture fetch / sampler cache) is the percentage of the
> time you're cache missing.
Il 29/03/2010 07:15, Zou, Nanhai ha scritto:
>>> 2010/3/26 Niccolò, Belli :
>>> Too bad :(
>>> When will I be able to test h264 decoding with a gma x4500?
> G45 support will come in Q3.
Is there any news?
___
Intel-gfx mailing list
Intel-gfx@lists.
On Thu, 07 Oct 2010 15:43:43 +1000, Dave Airlie wrote:
> On Wed, 2010-10-06 at 21:24 -0700, Keith Packard wrote:
> > A physically mapped hardware status page is allocated at driver load
> > time but was never freed. Call the existing code to free this page at
> > driver unload time on hardware whi
On Wed, 6 Oct 2010 22:57:49 -0700, milk wrote:
> I recently purchased a Shuttle SH55J2 which has the Intel H55 chipset
> (Auburndale). Using xf86-video-intel-2.12.0-3 for arch linux, I am
> having KMS issues with the VGA/HDMI output. With KMS enabled, the VGA
> output is wavey and unreadable and t
Vincent wrote on Thursday, October 07, 2010 3:48 PM:
> Dear Gordon,
> Thanks for help!
> I can't see Q57 on readme file. it only shows these chipsets:
>
> i810/i810e/i810-dc100,i815,
> i830M,845G,852GM,855GM,865G,
> 915G/GM,945G/GM/GME,946GZ
> G/GM/GME/Q965,
> G/Q33,G/Q35,G41,G/Q43,G/GM/Q45
>
Dear Gordon,
Thanks for help!
I can't see Q57 on readme file. it only shows these chipsets:
i810/i810e/i810-dc100,i815,
i830M,845G,852GM,855GM,865G,
915G/GM,945G/GM/GME,946GZ
G/GM/GME/Q965,
G/Q33,G/Q35,G41,G/Q43,G/GM/Q45
PineView-M (Atom N400 series)
PineView-D (Atom D400/D500 series)
And, could
On Thu, Oct 7, 2010 at 12:06 AM, Jin, Gordon wrote:
> Which kernel are you using? You might want to try the latest rc kernel.
I am running from a stock arch linux install which is using kernel26
2.6.35.7-1, which looks to be the latest version as kernel.org.
-milki
--
Hope is a dimension of
Vincent wrote on Wednesday, October 06, 2010 2:36 PM:
> Dear Sir,
> Could you help to find Q57 VGA and chipset driver for Linux?
It has been supported since http://intellinuxgraphics.org/2010Q1.html
(mentioned as HD Graphics or Clarkdale). Better to use the latest version:
http://intellinuxgraph
milk wrote on Thursday, October 07, 2010 1:58 PM:
> I recently purchased a Shuttle SH55J2 which has the Intel H55 chipset
> (Auburndale). Using xf86-video-intel-2.12.0-3 for arch linux, I am
> having KMS issues with the VGA/HDMI output. With KMS enabled, the VGA
> output is wavey and unreadable and
42 matches
Mail list logo
