Re: [Intel-gfx] Interrupt latency on some 945GM platforms

2010-09-16 Thread Vasily Khoruzhick
В сообщении от 16 of September 2010 21:50:50 автор Thomas Gleixner написал: > Ok. The problematic part of HPET was not the clocksource, it was the > clock event device which failed to deliver interrupts occasionally. It > was worth a try at least. Hm, it seems that jerky glxgears is not related to

Re: [Intel-gfx] Interrupt latency on some 945GM platforms

2010-09-16 Thread Vasily Khoruzhick
В сообщении от 16 of September 2010 21:30:58 автор Vasily Khoruzhick написал: > В сообщении от 16 of September 2010 21:07:39 автор Thomas Gleixner написал: > > > Btw, Jesse, any comments/solutions/workarounds except one with > > > processor.max_cstate=1 in kernel commandline? Should I file a bug on

Re: [Intel-gfx] Interrupt latency on some 945GM platforms

2010-09-16 Thread Vasily Khoruzhick
В сообщении от 16 of September 2010 21:07:39 автор Thomas Gleixner написал: > > Btw, Jesse, any comments/solutions/workarounds except one with > > processor.max_cstate=1 in kernel commandline? Should I file a bug on fdo > > bugzilla? > > we fixed a HPET related bug a few days ago, which might be

Re: [Intel-gfx] Interrupt latency on some 945GM platforms

2010-09-16 Thread Vasily Khoruzhick
В сообщении от 15 of September 2010 01:41:11 автор Sitsofe Wheeler написал: > > > processor.max_cstate=2 > > > > Nope, it doesn't work with max_cstate=2 > > Perhaps intel_idle is being used? Any mention of it in dmesg? Sitsofe, maybe you misunderstood me, I mean with max_cstate=1 graphics is

Re: [Intel-gfx] [PATCH][v2] drm/1915: save the right fence registers for Sandybridge

2010-09-16 Thread Liu, Yuanhan
> > You have a typo in the title. It should be drm/i915, not drm/1915. Oops, A fixed version is sent. Thanks. > > Geir Ove ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] [v3] drm/i915: save the right fence registers for Sandybridge

2010-09-16 Thread Yuanhan Liu
Sandybridge uses different address offset(0x10) for fence table registers, so make sure we have the right fence registers saved before suspend. This would fix bug: https://bugs.freedesktop.org/show_bug.cgi?id=30199 Cc: sta...@kernel.org Signed-off-by: Yuanhan Liu --- drivers/gpu/drm/i915/i9

Re: [Intel-gfx] [PATCH][v2] drm/1915: save the right fence registers for Sandybridge

2010-09-16 Thread Geir Ove Myhr
You have a typo in the title. It should be drm/i915, not drm/1915. Geir Ove ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH][v2] drm/1915: save the right fence registers for Sandybridge

2010-09-16 Thread Yuanhan Liu
Sandybridge uses different address offset(0x10) for fence table registers, so make sure we have the right fence registers saved before suspend. This would fix bug: https://bugs.freedesktop.org/show_bug.cgi?id=30199 Cc: sta...@kernel.org Signed-off-by: Yuanhan Liu --- drivers/gpu/drm/i915/i9

Re: [Intel-gfx] [PATCH] drm/1915: save the right fence registers for Sandybridge

2010-09-16 Thread Zhenyu Wang
On 2010.09.16 15:59:29 +0800, Yuanhan Liu wrote: > Sandybridge uses different address offset(0x10) for fence table registers, > so make sure we save the right fence registers before suspend. > > This would fix bug: https://bugs.freedesktop.org/show_bug.cgi?id=30199 > Nice catch! But fence re

[Intel-gfx] [PATCH] drm/1915: save the right fence registers for Sandybridge

2010-09-16 Thread Yuanhan Liu
Sandybridge uses different address offset(0x10) for fence table registers, so make sure we save the right fence registers before suspend. This would fix bug: https://bugs.freedesktop.org/show_bug.cgi?id=30199 Signed-off-by: Yuanhan Liu --- drivers/gpu/drm/i915/i915_suspend.c | 10