Hi,
I think there may be a possibility of compilation error with drm-intel
commit 6ef3d42 if CONFIG_DEBUG_FS isn't selected.
commit 6ef3d4278034982c13df87c4a51e0445f762d316
Author: Chris Wilson
Date: Wed Aug 4 20:26:07 2010 +0100
drm/i915: Capture the overlay status upon a GPU hang.
Signed-off-by: Zhenyu Wang
---
drivers/char/agp/intel-agp.c|2 ++
drivers/char/agp/intel-agp.h|1 +
drivers/gpu/drm/i915/i915_drv.c |1 +
3 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index ab19039..7
This one is missed in last pipe control fix for sandybridge,
that really unmask interrupt bit for notify in render engine IMR.
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/i915_irq.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_i
Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC. This one trys to setup a
new gtt driver for Gen6, and using new type mask function for that.
And this sets cache control to always LLC only by default on Gen6.
As this gtt memory cache control
Signed-off-by: Zhenyu Wang
---
drivers/char/agp/intel-agp.c | 24 +++-
1 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index ddf5def..ab19039 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/c
On Wed, Aug 18, 2010 at 5:05 PM, Jesse Barnes wrote:
> On Wed, 18 Aug 2010 21:48:50 +0100
> Owain Ainsworth wrote:
>
>> On Wed, Aug 18, 2010 at 12:00:36PM -0700, Jesse Barnes wrote:
>> > Waiting for a hard coded 20ms isn't always enough to make sure a vblank
>> > period has actually occurred, so
On Wed, 18 Aug 2010 21:48:50 +0100
Owain Ainsworth wrote:
> On Wed, Aug 18, 2010 at 12:00:36PM -0700, Jesse Barnes wrote:
> > Waiting for a hard coded 20ms isn't always enough to make sure a vblank
> > period has actually occurred, so add code to make sure we really have
> > passed through a vbla
On Wed, Aug 18, 2010 at 12:00:36PM -0700, Jesse Barnes wrote:
> Waiting for a hard coded 20ms isn't always enough to make sure a vblank
> period has actually occurred, so add code to make sure we really have
> passed through a vblank period (or that the pipe is off when disabling).
>
> This preven
On Wed, 18 Aug 2010 12:00:29 -0700
Jesse Barnes wrote:
> This set replaces the last one, and includes an additional patch to fix
> our vblank wait code, which is apparently important especially when
> dealing with link training.
>
> It also contains a patch to address Adam's comment about the ne
On Wed, 2010-08-18 at 12:00 -0700, Jesse Barnes wrote:
> This set replaces the last one, and includes an additional patch to fix
> our vblank wait code, which is apparently important especially when
> dealing with link training.
I always did hate that msleep.
Reviewed-by: Adam Jackson
for the s
Waiting for a hard coded 20ms isn't always enough to make sure a vblank
period has actually occurred, so add code to make sure we really have
passed through a vblank period (or that the pipe is off when disabling).
This prevents problems with mode setting and link training, and seems to
fix a bug
---
drivers/gpu/drm/i915/intel_display.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6dab095..928bcc2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel
We need to make sure the eDP PLL is enabled before the pipes or planes,
so do it as part of the DP prepare mode set function.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 39 +
drivers/gpu/drm/i915/intel_dp.c | 63 +++
Useful for capturing register read/write traces to send to the hw guys.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 30 --
1 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i9
We need to use I/O port instructions to access VGA registers on
Ironlake+, and it doesn't hurt on other platforms, so switch the VGA
plane disable function over to using them. Move it to init time as well
while we're at it, no need to repeatedly disable the VGA plane with
every mode set and DPMS e
We should disable the panel first when shutting down an eDP link. And
when turning one on, the panel needs to be enabled before link training
or eDP I/O won't be enabled.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 15 ---
1 files changed, 8 insertions(+), 7
Ironlake requires that we clear the reset panel bit during power
sequences and restore it afterwards. Uncondtionally add code to do that
since it should be harmless on SNB+.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 17 -
1 files changed, 16 insertions(
This set replaces the last one, and includes an additional patch to fix
our vblank wait code, which is apparently important especially when
dealing with link training.
It also contains a patch to address Adam's comment about the new VGA
disable code. I was missing a vga get/put pair around my acc
On Wed, 18 Aug 2010 10:28:24 +0100, Chris Wilson
wrote:
> Marty Jack reported an issue he found where the page-flipping handler
> was being lost on server reset. This results in the swap completion
> notification being lost, with the sporadic hang of full screen
> applications like Compiz, flash
Marty Jack reported an issue he found where the page-flipping handler
was being lost on server reset. This results in the swap completion
notification being lost, with the sporadic hang of full screen
applications like Compiz, flash and even glxgears!
Fixes:
Bug 29584 - Server in compute loop
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