Re: [Intel-gfx] [intel-gfx][PATCH] intel: add a new interface drm_intel_bo_alloc_direct

2010-05-26 Thread Xiang, Haihao
On Thu, 2010-05-27 at 04:52 +0800, Eric Anholt wrote: > On Tue, 25 May 2010 13:06:50 +0800, "Xiang, Haihao" > wrote: > > This interface is the same as drm_intel_bo_alloc except the allocated > > size isn't rounded up, so it bypasses the cache bucket. > > > > The size of the BO created by drm_in

[Intel-gfx] [RFC PATCH] agp/intel: Fix cache control for Sandybridge

2010-05-26 Thread Zhenyu Wang
Sandybridge GTT has new cache control bits in PTE, which controls graphics page cache in LLC or LLC/MLC. This one trys to setup a new gtt driver for Gen6, and using new type mask function for that. And this sets cache control to always LLC only by default on Gen6. As this gtt memory cache control

[Intel-gfx] [PATCH 2/2] drm/i915: Unmask interrupt for render engine on Sandybridge

2010-05-26 Thread Zhenyu Wang
With splitted engines on Sandybridge, each engine has its own interrupt control as well. This unmasks the interrupt to properly enable pipe control notify event for render engine. Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_debugfs.c |4 drivers/gpu/drm/i915/i915_irq.c

[Intel-gfx] [PATCH 1/2] drm/i915: Fix PIPE_CONTROL command on Sandybridge

2010-05-26 Thread Zhenyu Wang
Sandybridge(Gen6) has new format for PIPE_CONTROL command, the flush and post-op control are in dword 1 now. This changes command length field for difference between Ironlake and Sandybridge. I tried to test this with noop request and issue PIPE_CONTROL command for each sequence and track notify i

Re: [Intel-gfx] [PATCH] drm/i915: Fix HDMI mode select for Cougarpoint PCH

2010-05-26 Thread Eric Anholt
On Wed, 12 May 2010 11:02:14 +0800, Zhenyu Wang wrote: > For real HDMI sink, CPT HDMI port has to set 'HDMI' mode flag > in order to make HDMI audio work correctly. > > This is required patch for drm/i915 to enable HDMI audio on CPT PCH, > ALSA patch is at > http://mailman.alsa-project.org/piper

Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: Add DPCD data to debug output

2010-05-26 Thread Eric Anholt
On Thu, 13 May 2010 14:45:43 -0400, Adam Jackson wrote: > Signed-off-by: Adam Jackson > --- > drivers/gpu/drm/i915/intel_dp.c |2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 78a75e8..a1a6785

Re: [Intel-gfx] [PATCH] drm/i915: Kill dangerous pending-flip debugging

2010-05-26 Thread Eric Anholt
On Sat, 15 May 2010 09:31:17 -0700, Jesse Barnes wrote: > On Sat, 15 May 2010 09:57:03 +0100 > Chris Wilson wrote: > > > We can, by virtue of a vblank interrupt firing in the middle of > > setting up the unpin work (i.e. after we set the unpin_work field and > > before we write to the ringbuffe

Re: [Intel-gfx] [PATCH] agp/intel: Restrict GTT mapping to valid range on i915 and i945

2010-05-26 Thread Eric Anholt
On Tue, 18 May 2010 12:24:51 +0100, Chris Wilson wrote: > References: > > Bug 15733 - Crash when accessing nonexistent GTT entries in i915 > https://bugzilla.kernel.org/show_bug.cgi?id=15733 > > On G33 and above, the size of the GTT space is determined by the GMCH > control register. Prior

Re: [Intel-gfx] [PATCH] agp/intel: Restrict GTT mapping to valid range on i915 and i945

2010-05-26 Thread Eric Anholt
On Tue, 18 May 2010 12:24:51 +0100, Chris Wilson wrote: > References: > > Bug 15733 - Crash when accessing nonexistent GTT entries in i915 > https://bugzilla.kernel.org/show_bug.cgi?id=15733 > > On G33 and above, the size of the GTT space is determined by the GMCH > control register. Prior

[Intel-gfx] [PATCH] drm/i915: Return the error code from init_hws()

2010-05-26 Thread Chris Wilson
Otherwise we indicate success in the event of failure and this will lead to an eventual OOPS. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.

Re: [Intel-gfx] [PATCH] drm/i915/gen4: Extra CRT hotplug paranoia

2010-05-26 Thread Eric Anholt
On Mon, 24 May 2010 16:46:29 -0400, Adam Jackson wrote: > Disable the CRT plug interrupt while doing the force cycle, explicitly > clear any CRT interrupt we may have generated, and restore when done. > Should mitigate interrupt storms from hotplug detection. Nice, I've been hoping someone would

Re: [Intel-gfx] [intel-gfx][PATCH] intel: add a new interface drm_intel_bo_alloc_direct

2010-05-26 Thread Eric Anholt
On Tue, 25 May 2010 13:06:50 +0800, "Xiang, Haihao" wrote: > This interface is the same as drm_intel_bo_alloc except the allocated > size isn't rounded up, so it bypasses the cache bucket. > > The size of the BO created by drm_intel_bo_alloc for a 1920x800,4:2:0 YUV > planar surface is 4M, it is

Re: [Intel-gfx] [2.6.34, patch] i915: fix lock imbalance on error path...

2010-05-26 Thread Eric Anholt
On Mon, 17 May 2010 14:23:52 +0100, Daniel J Blueman wrote: > While investigating Intel i5 Arrandale GPU lockups with -rc4, I > noticed a lock imbalance. > > Signed-off-by: Daniel J Blueman Applied. Thanks! pgpI2j3wFbsWY.pgp Description: PGP signature ___

Re: [Intel-gfx] [PATCH] drm/i915: add timeout to FBC disable waits

2010-05-26 Thread Eric Anholt
On Fri, 21 May 2010 09:40:45 -0700, Jesse Barnes wrote: > FBC disable on 965 can take long enough to trigger latency checks in the > kernel so be sure to timeout after a reasonable period. > > Fixes https://bugzilla.kernel.org/show_bug.cgi?id=15015. > > Tested-by: James Ettle > Signed-off-by: