Re: [Intel-gfx] Intel/Pineview graphics won't load 1024x600 resolution in X11

2010-04-27 Thread Tino Keitel
On Tue, Apr 27, 2010 at 12:53:59 -0500, Gabriel M. Beddingfield wrote: > > Hello, > > First: if this is the wrong place to ask, would you please point me > to the appropriate channel. > > I'm using an N450 processor with the GMA 3150 Pineview graphics > system. When X11 starts, it seems to dete

Re: [Intel-gfx] [PATCH] drm/i915: Fix DDC bus selection for multifunction SDVO

2010-04-27 Thread Zhenyu Wang
On 2010.04.23 16:16:12 -0400, Adam Jackson wrote: > Multifunction SDVO cards stopped working after 14571b4, and would report > something that looked remarkably like an ADD2 SPD ROM instead of EDID. > This appears to be because DDC bus selection was utterly horked by that > commit; controlled_output

Re: [Intel-gfx] [PATCH 0/4] Attempt to re-enable FBC on gen3

2010-04-27 Thread Alexander Lam
On Fri, Apr 23, 2010 at 11:17 AM, Adam Jackson wrote: > Disclaimer: I haven't tested this extensively, it just seems logical, and I > really hate to see us lose FBC on gen3 since that's the family being used in > low-wattage devices.  Wider testing would be greatly appreciated. Seems to work here

Re: [Intel-gfx] Intel/Pineview graphics won't load 1024x600 resolution in X11

2010-04-27 Thread Adam Jackson
On Tue, 2010-04-27 at 14:58 -0500, Gabriel M. Beddingfield wrote: > First: I _really_ appreciate your help! > > I added 8086A010, 8086A011, and 8086A012 to a file > /usr/share/xserver-xorg/pci/intel.icv, and then I get: > > (EE) Failed to load module "i810" (module does not exist, 0) >

Re: [Intel-gfx] Intel/Pineview graphics won't load 1024x600 resolution in X11

2010-04-27 Thread Gabriel M. Beddingfield
On Tue, 27 Apr 2010, Adam Jackson wrote: On Tue, 2010-04-27 at 14:16 -0500, Gabriel M. Beddingfield wrote: On Tue, 27 Apr 2010, Adam Jackson wrote: On Tue, 2010-04-27 at 12:53 -0500, Gabriel M. Beddingfield wrote: Any idea why it won't load the correct resolution? Because you're using the

Re: [Intel-gfx] Intel/Pineview graphics won't load 1024x600 resolution in X11

2010-04-27 Thread Adam Jackson
On Tue, 2010-04-27 at 14:16 -0500, Gabriel M. Beddingfield wrote: > On Tue, 27 Apr 2010, Adam Jackson wrote: > > On Tue, 2010-04-27 at 12:53 -0500, Gabriel M. Beddingfield wrote: > >> Any idea why it won't load the correct resolution? > > > > Because you're using the vesa driver, and you should be

Re: [Intel-gfx] Intel/Pineview graphics won't load 1024x600 resolution in X11

2010-04-27 Thread Gabriel M. Beddingfield
On Tue, 27 Apr 2010, Adam Jackson wrote: On Tue, 2010-04-27 at 12:53 -0500, Gabriel M. Beddingfield wrote: Any idea why it won't load the correct resolution? Because you're using the vesa driver, and you should be using the intel driver. How do I get/force it to use the intel driver? I

Re: [Intel-gfx] Intel/Pineview graphics won't load 1024x600 resolution in X11

2010-04-27 Thread Adam Jackson
On Tue, 2010-04-27 at 12:53 -0500, Gabriel M. Beddingfield wrote: > Any idea why it won't load the correct resolution? Because you're using the vesa driver, and you should be using the intel driver. - ajax signature.asc Description: This is a digitally signed message part _

[Intel-gfx] [PATCH] Revert "drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on)."

2010-04-27 Thread Carl Worth
This reverts commit cfecde435dda78248d6fcdc424bed68d5db6be0b. The commit was first created as an attempt to fix LVDS initialiazation on Ironlake. Testing revealed that it didn't fix that, but it was assumed to still be correct anyway. Subsequent testing has revealed that this commit has caused ot

[Intel-gfx] Intel/Pineview graphics won't load 1024x600 resolution in X11

2010-04-27 Thread Gabriel M. Beddingfield
Hello, First: if this is the wrong place to ask, would you please point me to the appropriate channel. I'm using an N450 processor with the GMA 3150 Pineview graphics system. When X11 starts, it seems to detect that it's capable of 1024x600, but then loads 800x600 instead. (II) VESA(0):

Re: [Intel-gfx] [PATCH 5/7] drm/i915: use vblank and vsync interrupts on 945

2010-04-27 Thread Jesse Barnes
On Fri, 26 Mar 2010 11:07:19 -0700 Jesse Barnes wrote: > On 945, vblank delivery alone seems unreliable. The PIPE*STAT bits get > set correctly, but interrupts occur at a low frequency relative to > refresh. If we enable VSYNC interrupts as well however (even though we > only check for VBLANK i

Re: [Intel-gfx] [PATCH 3/3] drm/intel: Use 10-bit palette properly, only store 129 entries

2010-04-27 Thread Adam Jackson
On Mon, 2010-04-26 at 23:24 +0100, Peter Clifton wrote: > --- > drivers/gpu/drm/i915/intel_display.c | 38 ++--- > drivers/gpu/drm/i915/intel_drv.h |2 +- > 2 files changed, 17 insertions(+), 23 deletions(-) Nak. This will break DirectColor visuals in X. Di

Re: [Intel-gfx] [PATCH] drm/intel: Set 8-bit gamma mode for the palette

2010-04-27 Thread Adam Jackson
On Mon, 2010-04-26 at 22:19 +0100, Peter Clifton wrote: > @@ -3439,11 +3442,16 @@ void intel_crtc_load_lut(struct drm_crtc *crtc) > > /* use legacy palette for Ironlake */ > if (IS_IRONLAKE(dev)) > - palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : > -