On Tue, 22 Jan 2019 at 07:44, John Gateley wrote:
> The link information in the 24-bit addressing mode consists of the
> instruction-length code (ILC), the condition code (CC), the program-mask
> bits, and the rightmost 24 bits of the updated instruction address.
>
> I have never given much tho
On Tue, 22 Jan 2019 17:13:04 +, Seymour J Metz wrote:
>I've used the CC bits but never the ILC bits.
>
I've used them to tell whether I was on 370 hardware or 31-bit mode on
XA hardware. I did not support 24-bit mode on XA hardware.
-- gil
--
I've used the CC bits but never the ILC bits.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Discussion List on behalf of
John Gateley
Sent: Tuesday, January 22, 2019 7:43 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: BALR and
: Re: BALR and BAL in AMODE=24
I wonder what the purpose of this is.
It branches to R14, usually the return address, unless you loaded the
destination address in R14 first.
I am used to BALR R14,15, where R15 is the (conventional) destination address.
Kees.
> -Original Message-
> Fro
Yes.
I have worked on application programs that interrogated the high order byte to
determine what logic path to take in the called routine.
In certain other cases it was used after return to the caller to look at the cc
from before the BAL/BALR and branch accordingly.
Sent from my iPhone
wab
Sent: 22 January 2019 15:30
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: BALR and BAL in AMODE=24
First thing is it loads the address of the next instruction into R14.
It then jumps to that location. Doesn't that cause some processors to
sync up the cache and instruction pipelines?
A BA
ntional) destination address.
>
> Kees.
>
>
> > -Original Message-
> > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> > Behalf Of esst...@juno.com
> > Sent: 22 January, 2019 14:31
> > To: IBM-MAIN@LISTSERV.UA.EDU
> > S
On Tue, 22 Jan 2019 06:43:54 -0600 John Gateley
wrote:
:>The link information in the 24-bit addressing mode consists of the
instruction-length code (ILC), the condition code (CC), the program-mask bits,
and the rightmost 24 bits of the updated instruction address.
:>I have never given much tho
n List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> Behalf Of esst...@juno.com
> Sent: 22 January, 2019 14:31
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: BALR and BAL in AMODE=24
>
> I remember back in the CICS/VS days we would code a BALR 14,14
> It was a great Interview question
I remember back in the CICS/VS days we would code a BALR 14,14
It was a great Interview question to explain the workings of a BALR instruction.
-- Original Message --
From: John Gateley
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: BALR and BAL in AMODE=24
Date: Tue, 22 Jan 2019 06:43:54
In the 370 days, thats how we used to establish addressability! A BALR to a
register with a zero in the link position merely loads the PSW instruction
address into a register, like this:
BALR 15,0
USING *,15
Joe
On Tue, Jan 22, 2019 at 6:44 AM John Gateley
wrote:
> Hello.
>
> The link informat
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