Hi Paul,
VSTBRH comes to mind - Vector STore Byte Reversed elements Halfword.
See PoP page 21-24 (or page 1678 of the PDF)
Not sure though, whether this qualifies as an endian accommodation to you.
Kind regards,
Abe Kornelis
==
On 07/07/2025 20:36, Paul Gilmartin wrote:
> On Mon
https://github.com/abekornelis/Bixite
Kind regards & happy programming!
Abe Kornelis
==
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send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
assembler, linker, and an execution
environment to run your application programs.
It also contains scriptable test and trace facilities,
zCobol, zCics, zSort, zVSAM, and much more.
Kind regards & happy programming,
Abe Korn
labels these different actions as "Nullified",
"Suppressed", "Completed", "Terminated", or "Unaffected".
See figure 6-1 for a complete overview.
Kind regards,
Abe Kornelis
==
On 03/05/2025 05:02, Johnny Luo wrote:
> Hi,
>
> Whe
speed of
55GHz.
Obviously, that limit of ten will rarely be reached, but only one at a
time is
probably rather rare as well these days.
I'd have liked to see some metrics from IBM testing, if only to please
the taste buds :-)
Kind regards & Happy programming,
Abe Kornelis
==
On 1
tool - more so since there are
options to port between environments.
Point in case, I am currently looking at porting large Rexx program from
z/OS to our distributed environment...
Kind regards,
Abe Kornelis.
===
On 01/04/2025 01:07, Steve Horein wrote:
> I used to feel clever
Peter,
I have little to add to all the laudations that others have already
bestowed on you.
It's been a pleasure working with you - before, after, and during my
short sojourn at IBM.
I wish you all the best and hope your days will be fruitful and happy.
Kind regards,
Abe Kor
to check SYS1.LOGREC if I remember correctly, to see the
abend data.
Kind regards,
Abe Kornelis
==
Op 26/11/2024 om 21:18 schreef Richard Zierdt:
> SCHEDULE and IEAMSCHD (recommended) services create an SRB, but how is the
> SRB called?
> The SRB is not invoked by IEAMSCHD. Or is it
Hi Richard,
with SSWITCH=NO, and the routine being invoked from various address spaces,
the routine should be loaded into common storage. Is it?
Probably not - the S0C4 in AddrSpace B attests to that.
I note you have STATE=SUPERVISOR.
This means you are authorizing all address spaces in your syst
> GitLab
**-- > Those folks are doing a lot of interesting stuff. But their
repository has only a very partial subset of the NIST test suite. :-(
I'll try to contact them. Thanks for the pointer :-)
Thanks again & kind regards,
Abe
===
>
>
> At 02:55 AM 10/4/20
.
Thanks in advance,
Abe Kornelis
==
PS: you can find more info about the z390 project on z390.org
and more info about the zCobol component on zcobol .org
Abe
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Geoff,
thanks for the quick reply.
I can see it's been documented.
The proof of the pudding would have been to see the
instruction being assembled correctly.
I'll take your word for it, HLASM will assemble it just fine.
Kind regards,
Abe Kornelis
Op 29/03/2018 om 17:
out details like these,
please make a mental note about the missing instruction.
Anybody care to double-check on HLASM being aware of the WFKHEXBS mnemonic?
Kind regards to you all,
Abe Kornelis
==
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Kind regards,
Abe Kornelis, z390 moderator
===
Op 21-2-2017 om 23:29 schreef Bill Woodger:
> "Define one or more directories for source MAC files. If the option starts
> with + the directories listed will be concatenat
27;ll have to find out for yourself.
Kind regards,
Abe Kornelis.
===
Lopez, Sharon schreef op 15-5-2015 om 19:54:
> What are the majority of companies using for their mainframe scheduling
> software? Any concerns with ASG (ZEKE/ZEBB) filin
.
If you have any info or pointers at that level, I would much appreciate
that!
Kind regards,
Abe Kornelis
==
Timothy Sipples schreef op 10-3-2015 om 7:43:
The vector new vector architecture looks interesting, but completely
different from the old vector architecture.
The IBM z13's
All,
I just downloaded the new version of the Principles of Operation
SA22-7832-10 from IBM.
The vector new vector architecture looks interesting, but completely
different from the old vector architecture.
Regards,
Abe Kornelis
on the new
instructions.
I am especially interested in the vector architecture and instructions.
To explain the vector architecture well, embellished with examples,
exercises and solutions,
you might end up with a volume that satisfies Lizette's desires?
Kind regards
Abe Kornelis
need a lock or latch of some kind after all. Or
pre-load, maybe.
I'm sure you'll be able to determine what will work best for your product.
Success!
Abe Kornelis
==
Gary Weinhold schreef op 21-1-2015 om 16:26:
We have a situation where it appears that a LOAD of a module m
code...
Kind regards,
Abe Kornelis
==
Don Poitras schreef op 19-1-2015 om 12:15:
Jeremy,
Thanks. I was able to see the page Friday afternoon. It's funny to
see all the vector instructions back again. Now we have to decide if
it's worth resurrecting the code that used them.
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