scoping of variables

This is a newbie question, so please bear with me if similar questions have been discussed before. I couldn't find anything in the list archives though. I'd like to build a big project that spawns several directories, but don't want to call make recursively because I read "Recursive Make Conside

RE: scoping of variables

> No, there is no such thing as variable scoping in GNU make. The sole > exception is for target- and pattern-specific variables, but that's > probably too fine-grained to be useful for your purposes. Ok, so it looks like emulating scoped variables through a stack is the way to go. > People ty

variable parameter list

Hi, consider this makefile: .PHONY: all all: sorted.tgt header.tgt reverse.tgt footer.tgt # The lines below are supposed to do this: #sorted.tgt: list1.lst list2.lst # cat $^ | sort >$@ #header.tgt: list1.lst list2.lst list3.lst # cat $^ | head >$@ #reverse.tgt: list1.lst # cat $^ | tac >$@ #foot

RE: variable parameter list

> Don't know if that's what you want but the simplest solution would be to > treat list of files a third parameter instead as separate arguments i.e. > > define FILTER_RULE > ${2}: ${3} > cat $$^ | ${1} >$$@ > endef > > all: sorted.tgt header.tgt reverse.tgt footer.tgt > > $(eval $(call F

RE: A question about Makefile

Jed Jia wrote: > Take a look at the following Makefile: > > > x: obj/./t > >     touch x > > > > obj/t: a > >     touch obj/t > > but make outputs: > > make: *** No rule to make target `obj/./t', needed by `x'.  Stop. While I'm not able to answer your final question, this function may help (take

Passing environment variables in reciepes

Hi, please consider the following makefile: all: @if [ "${USER}" == "" ]; then \ export message="no user defined"; \ else \ export message="user is ${USER}"; \ fi @echo ${message} $${message} $message $$message eval $$message My problem ist

RE: A question about Makefile

Jed Jia wrote: > It works well, but seems a little inconvenient. Do I have to use > CANONICAL_PATH on every file path? Yeah, it doesn't make the makefile more readable. You must use it whenever there is a risk that the path is not in its canonical form. > And I wonder whether this is a

RE: Passing environment variables in reciepes

David Boyce wrote: > You're barking up the wrong tree. Each line of the recipe is passed by > make to a separate instance of the shell. Each of these processes is > the child of make, thus making them siblings. Environment variables > won't work for the same reason you can't inherit a trait from yo

RE: Passing environment variables in reciepes

Kristof Provost wrote: > Each line in the recipe is executed in its own shell. > If you add '; \' behind the 'fi', so echo is executed in the same shell > as the if statement you'll have a different result. Yeah, I should have tried this myself! My misconception was that I thought that exportin

RE: Passing environment variables in reciepes

David Boyce wrote: > Though it doesn't matter in this case, using ";" to join lines is a > bad and way-too-common pattern because it breaks basic make semantics. > Normally in the case > > target: > line 1 > line 2 > > make will fail if line 1 fails. Joining lines with ";" will ch

RE: How does $(error) work?

Chris Cross wrote: > Trying to understand how $(error) works. The manual says "error is > generated whenever this function is evaluated." With the makefile below I > would expect to see output from line1 of the recipe but only see output > from $(error). > # error.mk > .PHONY: target > > target:

wildcard dependency

Hi, I need to ensure that a certain tool is generated before any reciepes are executed for a certain extension. To better understand what I need, consider the following makefile: xxx.ext: ./tool xxx.ext: tool # This works as expected. #$(wildcard *.ext: tool) # Why doesn't this cause "tool

hidden dependencies

Hi, I had to write a new build system using GNU make only for a rather complex and big project which had a really werid and unmaintainable build system nailed up from a bunch of perl scripts and a few makefiles. As everything was almost finished now, I just gave GNU make's -j option a try. Doi

RE: hidden dependencies

> If you are using recursive make then the answer is no it is not possible > even on "make level" > google for document "Recursive Make Considered Harmful" your parallel > builds will randomly fail > and the risk of failing will increase as you increase number of jobs. I read this document quite

RE: hidden dependencies

> I think you should look at Audited Objects > (http://audited-objects.sourceforge.net/) and in particular at its > dependency generation feature > (http://audited-objects.sourceforge.net/html/man/ao-howto.html#dependency_generation). > This does automatic discovery of all dependency information wi

RE: hidden dependencies

> Let me know your results, good or bad. Also note that the only > 'supported' platforms right now are Linux and Solaris, though it's > buildable on other systems. I certainly will, having to get it up and running under Cygwin first, as our tool chain runs under Windoze. ___

RE: Delegate Variable to sub-target

Anja Schäfer wrote: > Is it possible at all to call sub-routines in make? Sort-of, you may want to look at http://www.gnu.org/software/make/manual/make.html#Call-Function ___ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo

EasyMake

As promised, here is the up to date version of EasyMake. Again, comments are welcome. Cheers, Chris -Original Message- From: help-make-bounces+christof.warlich=siemens@gnu.org [mailto:help-make-bounces+christof.warlich=siemens@gnu.org] On Behalf Of Christof Warlich Sent: Sonnt

RE: How to limit the assignment of variable from command line only to the current makefile?

> The variable assigned in the parent makefile will be carried on to the > child makefile. This is only true if the variable is exported (export XXX:=abc) or, as in your example, if it is passed as a command line parameter. > I'm wondering if there is a way to localize this > effect only to the pa

How to stop make when an error occurs in a for loop?

Hi, please consider the following example: all: @for i in false true; do\ if ! eval $$i; then\ echo We leave the loop when $$i is called, but ...;\ false;\ break;\ fi;\ done; @echo ... the exit status is always $$?. So how can I caus

RE: How to stop make when an error occurs in a for loop?

> > So how can I cause make to stop when a failure occurs inside a for > > loop? > Use "exit 1" instead of "false; break;" Oh, yaeh, thanks! Looks like I missed the most obvious. ___ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman

eval: logic behind when to escape

Hi, please consider the following makefile: ifeq (0,$(MAKELEVEL)) all: ; $(MAKE) --no-print-dir else $(foreach i,all,\ $(eval $(i): ; @echo $(MAKEFLAGS))\ ) endif If this is called with e.g. make -j $(MAKEFLAGS) _does_ contain the --no-print-dir flag, but it seems that it doesn't cont

RE: eval: logic behind when to escape

> Maybe the following link will help you. > http://lists.gnu.org/archive/html/help-make/2007-07/msg00050.html Thanks for the link, the description from Philip w.r.t. variable expansion and evaluation is very worthwhile to read and helped me to understand what's going on: First, here is my (slight

RE: How to detect program path?

Is it just a search for an (executable) file that you are looking for? Then this may do the job: EXECUTABLE:=$(shell find / -name yourExecutable) But note that this is rather slow and may yield more that one location. -Original Message- From: help-make-bounces+christof.warlich=siemens.

colon in prerequisites?!

Hi, i have to port a build to CygWin, and I need to use a few windows tools in my reciepes that don't understand absolute Cygwin paths (i.e. something like /cygdrive/d/myifle or /home/christof/myfile). Fortunately, CygWin offers the cygpath tool, which converts pathes into a more windowish styl

performance problems under CYGWIN

Hi, I've written a complex and generic Makefile to deal with a rather huge project. While I started the development under Linux, I ultimately had to move to Windows as this is our development platform. But now, my problem is that any reciepe that Make executes has a 2 to 3 second delay before it

RE: performance problems under CYGWIN

>On 2011-09-16 15:00, Warlich, Christof wrote: >[...] >>> Invoking recipe from >>> /cygdrive/d/views/d7ks01_v6.21.01_ADWACH13/D7_ERL_D7KS_SRC_01/Makefile:823 >>> to update target >>> `Cpu555/_fa_gmc.a/d7ks01/dlr1/f/fa/src/spline.dat.o'. >>&

RE: performance problems under CYGWIN

David Boyce wrote: > wrote: >> Can anyone give me a hint as to why the delay may occur after the two "child >> access "lines above? > Sorry, I can't, but a few things: > > - What version of GNU make are you using? It came up very recently > that 3.82 has a bug which causes it to do exponentiall

RE: performance problems under CYGWIN

Hi, just to sum up on the topic: The final reason for the immense performance hit was an "export" statement, i.e. exporting everything to a submake from the parent make. Interestingly, this caused the long delay in the submake. Thus, with Cygwin, don't use a plain export in a Makefile but ony ex

overriding recipe

Hi, is it possible to override a rule without getting the "overriding recipe" warning? Some background on why I need that: I'm having a generic Makefile that includes a User.mk to allow user specific settings through variables and rules. The surrounding Makefile basically takes care to allow

list of targets

Hi, ... and a second question: like .VARIABLES contains a list of all make variables, is there a similar variable that contains a list of all targets? Cheers, Chris ___ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/he

RE: make always builds, part 2

Try making the $(OBJDIRECTORY) dependency an "order-only" dependency (see http://www.gnu.org/s/hello/manual/make/Prerequisite-Types.html, i.e. note the pipe character below): %.d : %.cpp | $(OBJDIRECTORY) g++ -MM -o $@ $< Hope this helps! Chris -Original Message- From: help-make-bou

RE: overriding recipe

> One simple thing is to create a sentinel variable specifying whether the > targets have been defined. > > So, in User.mk you'd do something like: > > FOO = foo > BAR = bar >... other variables ... > > ifndef TARGETS_DEFINED > TARGETS_DEFINED

here document in recipe

Hi, is it possible to have a here document to be executed by Make as a recipe? E.g, the following passes two commands to be executed on a "remote" host: ssh root@localhost

RE: here document in recipe

That avoids the need for the redirection on every line and the final copy, thanks. But the echos still bother me. I played arround with canned recipes, but without success. So it seems that this is the best one can get. -Original Message- From: help-make-bounces+christof.warlich=siemens..

Re: list of targets

On Tue, 2011-11-15 at 07:59:20 -0500 Paul Smith wrote: > On Tue, 2011-11-15 at 12:12 +0100, Warlich, Christof wrote: > > like .VARIABLES contains a list of all make variables, is there a > > similar variable that contains a list of all targets? > > No. I had an implemen

RE: Make detects warning as errors

This is most probably not due to make, but due to your compiler: Have you checked the exit code of the call to fcc907s? Anything else but a zero exit code will cause make to stop. I'm just guessing here, but check the command line options -w 6 and -cwno, maybe one of them causes your compiler to e

.DELETE_ON_ERROR

Hi, it looks like the target of a rule is not deleted in case of an error within that rule and in the presence of a .DELETE_ON_ERROR target if that target is a directory. Is there a way to change this, i.e. to make Make to also delete targets if they are directories (possibly with content)? Is

RE: Make doesn't understand wich files have been modified

Header dependencies are not automatically seem by make; external tools (typically the compiler, the preprocessor or makedepend) must deduce these dependencies and tell make, usually through generated .mk files that are included by your makefile. A very god and elaborate hans-on on this topic may b

RE: Re: list of targets

Sorry for being importunate w.r.t. this, but just in case my question slipped while more important work was due: Is there any chance for a .TARGETS variable in the upcomming release of make? From: Warlich, Christof Sent: Donnerstag, 24. November 2011 14:11 To

RE: Re: list of targets

> There's always a chance, but the issue is a bit tricky: Ok, thanks, so I wouldn't loose hope ... :-) ___ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/help-make

RE: .DELETE_ON_ERROR

To me, not deleting directories in this scenario looks like a flaw. Do you agree? Is it going to be fixed? From: Warlich, Christof Sent: Freitag, 25. November 2011 09:04 To: help-make@gnu.org Subject: .DELETE_ON_ERROR Hi, it looks like the target of a rule is

RE: here document in recipe

GS as scoped variables). Thanks a lot for sharing this! Cheers, Chris -Original Message- From: David Boyce [mailto:david.s.bo...@gmail.com] Sent: Dienstag, 6. Dezember 2011 05:02 To: Warlich, Christof Cc: Stephan Beal; make-h...@gnu.org Subject: Re: here document in recipe On Nov 22,

reparsing makefile

Hi, please consider the following Makefile: /mnt/xxx: xxx | /mnt/mounted cp $< $@ /mnt/mounted: mount -t cifs -o password=siemens //localhost/share /mnt touch $@ It seems to work fine at the first glance: # make mount -t cifs //localhost/share /mnt touch /mnt/mounted cp

RE: reparsing makefile

> > Thus, I need to reparse the Makefile whenever mounting was needed. > An include file might help you with that. I reread the section about the include directive in the manual, but I'm not sure if I really understand: As the whole point is about reparsing, I assume you refer to make's abilit

RE: reparsing makefile

> > Warlich, Christof wrote: > > > > > > > Thus, I need to reparse the Makefile whenever mounting was > > > > > needed. > > > > > >> An include file might help you with that. > > > > > > I reread the sect

make similar to rsync -r -t --del

Hi, using rsync, it is rather simple to synchronize two directories: $ rsync -r -t --del sourcedir/ destdir In this example, if a file is deleted fron sourcedir, it also gets deleted from destdir. Any other files are updated as needed. I want to accomplish almost the same with Make, but instea

database buildup and reciepe execution

Hi, consider the following makefile: .PHONY: all all: PT xxx xxx: yyy ; cp $< $@ .PHONY: PT PT: ; touch xxx As much as I thought I understood, make _first_ builds up its database to determine what to do, and _then_ executes the recipes accoding to that result. But unfortunately, my understandi

RE: database buildup and reciepe execution

> But unfortunately, my understanding doesn't match the behaviour in the > example above ... Ok, make -d gave me some insight ... Make seems to run recipes immediately after it knows everything that needs to be done for that paricular rule _before_ looking ahead for the next dependency.

RE: database buildup and reciepe execution

> I'm not sure what you mean by "immediately after", but this doesn't > sound right (it could be a terminology thing). See if my comments above > clarify things. Yes they do, thanks a lot! ___ Help-make mailing list Help-make@gnu.org https://lists.gnu.o

$(MAKEFLAGS) and -j

Hi, from the manual: > The ‘-j’ option is a special case (see Parallel > Execution). If > you set it to some numeric value ‘N’ > and your operating system supports it (most any UNIX system will; others > typically won't), the > parent

RE: $(MAKEFLAGS) and -j

Hi, is there really no way to find out from within a Makefile whether the -j option was set? And if so, shouldn't at least the documentation be updated accordingly? Cheers, Chris From: Warlich, Christof Sent: Montag, 27. Februar 2012 16:46 To: help

Avoid generation of include files when doing "make clean"

Hi, please consider the following Makefile: -include xxx.inc xxx.inc: ; echo 'dosomething: ; touch $$@' >$@ .PHONY: clean clean: ; rm -f xxx.inc dosomething It works fine when I call 'make' and then 'make clean'. But when I call 'make clean' a second time, it generated the include

RE: Avoid generation of include files when doing "make clean"

ake-h...@gnu.org Subject: Re: Avoid generation of include files when doing "make clean" On Wed, Apr 4, 2012 at 12:20 PM, Warlich, Christof < christof.warl...@siemens.com> wrote: > It works fine when I call 'make' and then 'make clean'. But when I call > '

RE: how to improve compactness?

Hi Matej, > In my Makefile, I have a series of lines like this: > > dir := src/foo-01 > include $(dir)/rules.mk > > dir := src/foo-02 > include $(dir)/rules.mk > > dir := src/foo-03 > include $(dir)/rules.mk > > ... > > As I add new and new foo-direct

RE: any example on "Generating Prerequisites Automatically"?

> The suggested method in GNU Make book generates one .d file for each > .c file in the c files directory, which seems a mess. How to generate > the .d files in another directory? What's the best practice using this > feature? Hi Michael, Just combine these blueprints: http://mad-scientist.net/

Make doesn't honor .SHELLFLAGS?

Hi, I'd like to have Make to use a shell that executes a specific init file. I tried the following, but it doesn't work: echo "echo -n Hello">xxx && make SHELL=/bin/bash .SHELLFLAGS="--init-file xxx -i -c" The Makefile may be as simple as: all: ; @echo " World" but I only see: $ make World

RE: Make doesn't honor .SHELLFLAGS?

hristof.warlich=siemens@gnu.org] On Behalf Of Greg Chicares Sent: Donnerstag, 25. Oktober 2012 10:41 To: help-make@gnu.org Subject: Re: Make doesn't honor .SHELLFLAGS? On 2012-10-25 06:57Z, Warlich, Christof wrote: > > I'd like to have Make to use a shell that executes a sp

unexpected behaviour with match anything rule

Hi, please consider the following Makefile: t1: ; @echo specific rule for target $@ ifeq (,$(UNEXPECTED)) %: ; @echo expected anything rule for target $@ else %: all ; all: ; @echo unextected anything rule for target $@ endif I very much like its behaviour in the ifeq clause, as only th

RE: unexpected behaviour with match anything rule

> I think this is correct behavior. Why do you think the rules for the 'all' > target should not be executed? The else part states that all targets matching > % depend on all, so its rules get run first. I'm just puzzled because of the _different_ behaviour in ifeq- and else clause: They only di

MAKEFLAGS

Hi, I'd like to check for the existence of some .mk files from my Makefile. As Make may find these .mk files through --include-dir=... flags, I'd also like to search these directories. The documentation says that this should be possible through the variable MAFEFLAGS: 5.7.3 Communicating Option

release of make 3.82.90?

Hi, are there any plans to release a version of make 3.82.90 (or any followup) any time soon? In using MinGW/Msys, where the latest released version (make 3.82) is unusable slow. make 3.82.90 obviously fixes that, but I'm somewhat hesitant using an "unofficial" build in a critical project. Th

include and reparsing Makefile

Hi, I'm seeing a rather unexpected behaviour when including a submakefile. Please consider the following Makefile: nothing: reparse.mk: mayOrMayNotExist ; @echo would remake $@ -include reparse.mk When I call make while the file mayOrMayNotExist does exist, I get: $ touch mayOrMayNotExist $ ma

RE: include and reparsing Makefile

ent is needed because reparse.mk is _initially_ not there. Anyhow, thanks a lot for your help. -Original Message- From: Paul Smith [mailto:psm...@gnu.org] Sent: Mittwoch, 17. April 2013 12:51 To: Warlich, Christof Cc: help-make@gnu.org Subject: Re: include and reparsing Makefile

AW: Looking for help improving performance (advice or potential contract position)

> Be sure, if you have auto-generated dependencies, that you're using the "new > method" and not the one documented in the GNU make manual which requires > re-invoking make That sounds interesting: The only way I know to generate dependencies is the one described in section 4.14 (Generating Pre

AW: Looking for help improving performance (advice or potential contract position)

Hi Paul, > > Be sure, if you have auto-generated dependencies, that you're using the > > "new method" and not the one documented in the GNU make manual which > > requires re-invoking make > > That sounds interesting: The only way I know to generate dependencies is the > one described in sectio

$(wildcard ) in fakechroot environment

Hi, I'm trying to get my toolchain builds up and running in a chroot environment to guarantee defined tools. I'm using fakechroot to avoid root privileges. Everything seems to be running fine, except that make's $(wildcard ) function does not work as expected: $ fakechroot chroot rootdir cat

AW: $(wildcard ) in fakechroot environment

Thanks a lot for reproducing the issue and for explaining its root cause. > I've long considered it would be a good idea to allow makefiles to disable > the cache if they wanted to, but such a capability hasn't been implemented. Wouldn’t it be enough to just invalidate the cache before calling $

AW: Exported vs command line variables

> There is no difference between the two. They both declare environment > variables for make. That's not entirely true, at least not for (admittedly rather ancient) GNU Make V3.81. E.g., consider this Makefile: var := $(shell echo "echo hi" >say_hi.sh; chmod +x say_hi.sh; say_hi.sh) all: ; @ech

AW: AW: Exported vs command line variables

> > I'm not sure though if this is intended behavior or just a bug > Well, actually I am using version 4.1 and I do see the difference, are > you sure it is not working as intended ? Well, as I said above, I'm definitely not sure. I would most likely consider it being a bug. Nevertheless, it's a

AW: AW: AW: Exported vs command line variables

> Is there a Make bug report where I could try to raise a bug ? See http://lmgtfy.com/?q=gnu+make+bug+reports :-) ___ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/help-make

refering to order-only prerequisite

Hi, please consider the following example Makefile: all: | some_order_only_prerequisite echo $< some_order_only_prerequisite: touch $@ I would have expected that running make would always print "some_order_only_prerequisite", but obviously, $< does not refer to the first depen