[gem5-users] How to obtain real-time cache information in FS simulation

Hello, I plan to enable my program to read hardware information from the underlying layer during full simulation, such as the hit rate of L1 cache, and then schedule based on this information. However, I am not sure how to implement it. My current idea is to add new instructions to Gem5 and impl

[gem5-users] Transfer cache information to misc register in arm

I am a beginner who has just started to learn Gem5. Recently, I attempted to use the msr instruction to read out the currently allocated entries in L2cache (variable "int allocated" in gem5 stable \ src \ mem \ cache \ queue.hh). I have added a new system register for this purpose (by modifying

[gem5-users] ARM Full simulation using O3CPU and Kernel panic in simulated kernel

Hi,team. Recently, I have been trying to conduct a full simulation experiment on ARM and running some benchmarks on it. Currently, I have encountered two issues. 1.First, I will use the following command line to full simulate ./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py --cache --boot

[gem5-users] About Running Parsec and SPEC2017 Benchmarks in Gem5 ARM FS Simulation

Hello, team! Recently, I have been trying to use the Parsec and spec2017 benchmarks in the tutorial in Gem5 ARM. However, I have seen in the tutorial that building images with specific benchmarks involves trying out specific. json configuration files. Due to my unfamiliarity with these configura