Hi all,
I am trying to learn how to implement cache coherence protocols in gem5 using
SLICC.
I am currently working on an MSI protocol, similar to the one described in the
gem5 book.
The protocol passes the random tester for X86
(`configs/learning_gem5/part3/ruby_test.py`), even when faced with
Hi Jason,
Thank you for your very helpful (and prompt) reply!
You were right that the SC_Failed was a red herring.
After playing around with my protocol a bit more, the issue seems to have been
that I was making the callback for load and store hits (e.g.
`sequencer.{x}Callback(address, entry, f
Hi all,
I am trying to run a Linux kernel in FS mode, with a custom-rolled SLICC/Ruby
directory-based cache coherence protocol, but it seems like the memory
controller is dropping some requests in rare circumstances -- possibly due to
it being overwhelmed with requests.
The protocol seems to w
Thank you (once again) for your helpful answers, Jason!
After having done some more experimenting following your suggestions, I've
found that increasing the deadlock threshold (by several orders of magnitude)
does not make the problem go away, nor does only increasing the number of
memory chann
Hey there folks,
I am trying to add an L2 between the directory and DRAM in a (otherwise flat)
SLICC protocol I've been working on but have been running into some issues. I
know that some of the example protocols in src/mem/ruby/protocol/ do have
co-located L3s alongside the directories, but to