[gem5-users] L1 Data Cache Ports

Hi. I am looking for a way to model and assess the impact of having one vs. two ports in the L1 data cache (e.g., cache serving two loads in the same cycle). I found two variables "*cacheLoadPorts*" and "*cacheStorePorts*", which are both set to 200 (surprinsingly) by default. There was some dis

[gem5-users] Set number of register file read and write ports

Hi, I'm trying to check the influence of the number of read and write register file ports on the maximum IPC achieved by the OoO model. However, I could not find any parameter that models the number of register file ports. Is there any? For example, in none of the methods chain: readIntRegOpera