[gem5-users] Wakeup after restoring checkpoint

It seems the wake up event of MyComponent is not registered successfully. But I am not sure about this... Based on this observation, my question is: - How to wake up your own component after restoring from a checkpoint? Best Regards == Yuan Yao (Mr.)

[gem5-users] How to change the router frequency in Garnet

with the PARSEC benchmark (currently I use CANNEAL, which is communication extensive), I get very little difference in terms of IPC. So, I think Router::checkReschedule() is not the right place for the router frequency tuning, is it? Best Regards == Yuan Yao

Re: [gem5-users] Wakeup after restoring checkpoint (Yuan Yao)

ctions in my component (You can see an example of how this method is used in the existing components). 3. I override the drainResume() method, and there, I schedule my periodic event. This way the periodic event works both with fresh execution, and with checkpoint resuming. I hope that this help

[gem5-users] PyGILState_Check() failure

Hi, We encountered the following error when I am using X86KvmCPU and TimingSimpleCPU to make checkpoints in FS. "pybind11::object_api<>::operator() PyGILState_Check() failure." The same problem is reproduced in Ubuntu 20.04 and 22.04. My guess is some simobjects grabbed the lo

[gem5-users] Error when compiling gem5

td::vector &&() && { return std::move(v); } Can anyone kindly give me a hint? I am using python-2.7.2, gcc-4.8.0, and scons-2.1.0, without system root privilege. I guess this error has something to do with the c++11 support, since the error is related to pybind11.

Re: [gem5-users] Error when compiling gem5

Hello Ciro, Thank you for your reply. Your way solves the problem. I am now using GCC 6.1.0 which compiles gem5 fine. Mr. Yuan Yao PhD Student ESY, ICT KTH Royal Institute of Technology <mailto:yuan...@kth.se> yuan...@kth.se <https://www.linkedin.com/in/yuan-yao-085

[gem5-users] ARM o3 cpu load operation block

this? I turn on RubySequencer,RubyPort,RubyQueue and find that there is an understanding request for the same cacheline of the load instruction, which seems to insert the later one into the retryList. Yuan Yao ___ gem5-users mailing list gem5-user

Re: [gem5-users] panic: Page table fault when accessing virtual address 0x9

Yuan Yao liked your message with Boxer. On Sun, Aug 11, 2013 at 08:41 AM, Xiangyang Guo wrote:HI, I'm sorry that the virtual address is 0x7dffe90. I made a mistake in my previous email. So could any one give me some hints? Thanks Xiangyang On Sat, Aug 10, 2013 at 5:12 PM, Xiangyan

[gem5-users] mandatory queue recycle function

Hi, all, I run some benchmarks with Ruby and O3CPU. As I look into the debug trace file, I find many line say "[Version 0, L1Cache, mandatoryQueue_in]: Recycling." After I grep "recycle()" function in src/mem folder, I find it's invoked in an action in SLICC files. e.g., the code snippet below

Re: [gem5-users] mandatory queue recycle function

nyone can shed more light on this? Yuan On 16 Aug, 2013, at 12:33 PM, Yuan Yao wrote: > Hi, all, > > I run some benchmarks with Ruby and O3CPU. As I look into the debug trace > file, I find many line say "[Version 0, L1Cache, mandatoryQueue_in]: > Recycling." After

[gem5-users] Ruby cache read/write ports

Hi, all, As I look through the code of Ruby, I see the Sequencer is connected with the SLICC generated L1 cache controller using a mandatory queue, from which the L1 controller would dequeue. My question is that does ruby have the notion of exclusive read, write and r/w ports? I need to implem

[gem5-users] Requests for the same cacheline in Ruby

Hi, all, I try to understand the mechanism Ruby uses to handle the case when a request comes by for the same cacheline to an outstanding request. As I look into the code, Ruby will kind of reject the later request, indicating that "the address is aliased". And the O3CPU gets this response and r

[gem5-users] Ruby SLICC vector type

Hi, all, How can I define a variable of vector type in SLICC? I tried to use std::vector but get errors. Any help is highly appreciated. Regards, Yuan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Uncacheable load panic

Dear all, I am experiencing the same problem to the thread posted before http://www.mail-archive.com/gem5-users@gem5.org/msg08426.html The panic shows during the "freeing init memory" stage of linux boot. Uncachable load [sn:e7b52] PC (0xc014e7a0=>0xc014e7a4).(0=>1) Has anyone fixed this? Best

Re: [gem5-users] About executing multi loads

I am experiencing the same issue. Wherever one CPU executes exit(), the muti-programmed simulation terminates. Anybody can help? On 11 Oct, 2013, at 1:14 AM, Rodrigo Reynolds Ramírez wrote: > Hello everyone; > > I am using gem5 for multi loads, I am using the below line for executing the >

Re: [gem5-users] About executing multi loads

gem5.org [mailto:gem5-users-boun...@gem5.org] On > Behalf Of Yuan Yao > Sent: Monday, October 21, 2013 2:00 PM > To: gem5 users mailing list > Subject: Re: [gem5-users] About executing multi loads > > I am experiencing the same issue. Wherever one CPU executes exit(), the > mu

[gem5-users] O3CPU LSQ store-to-load forwarding

Hi, all, Does the O3CPU LSQ support store-to-load forwarding? From the L1 memory trace, I can see a load issued to memory for exactly the same address (no only the cacheline address) to an outstanding store. Regards, Yuan ___ gem5-users mailing list g

Re: [gem5-users] O3CPU LSQ store-to-load forwarding

of store queue. > Anyone please correct me if I am wrong. Thanks! > > Zhiguo > > -Original Message- > From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On > Behalf Of Yuan Yao > Sent: Friday, October 25, 2013 5:00 PM > To: gem5 users mailing

[gem5-users] Anyone use Garnet standalone?

creator of Garnet, Niket. So if you guys happen to have this tester file, i think the name is tester-network-only.tgz , could you please send it to me through my private email? Thanks! Best Regards == Yuan Yao, Master Student of System-on-Chip (SoC), KTH

[gem5-users] How many event queues in Garnet?

Hello Dear All: Wish you all good. I'm new to gems. And here i want to ask two simple questions. 1, How many event queues are there in Garnet? Since garnet is a event driven network model, are all the events stored in a single global event queue? 2, How the events are fetched f

[gem5-users] Cache Transition Problem

Hello All: I use Gems + Simics 3.0 I compile Ruby with Garnet and it runs well when I use 16 cores. But when I configure Ruby to 64 cores, I got the following error when I run tester.exec: Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cac

[gem5-users] Re: Squashing Instructions after Page Table Fault

Hi Robin, If I understand it correctly, a Page Table Fault instruction is not squashed but *not executed*. The instruction generating a fault is marked ready to commit. Then, during the commit phase, the fault generated by the instruction is handled. To explain this in more detail let m

[gem5-users] Re: Squashing Instructions after Page Table Fault

Hi Robin, The "Page-Fault" message is printed out on the constructor of a fault, so gdb that line and move up frames can help. By the way, a page fault can also be generated during page walks (see here

[gem5-users] Re: Microcode_ROM Instruction and fetchRomMicroop() Function

Hi, The ROM contains predefined micro-code routines for purposes such as apic interrupt handler (arch/x86/isa/insts/romutil.py). If you are simulating a full system then basically the interrupt is triggered by 8254 timer (dev/x86/i8254.py) and when it is triggered the core fetches instr

[gem5-users] Re: Fixed I/O Address Range in x86

Hi Sam, ''scons build/x86/out/m5 --verbose'' shows ``` g++ -o build/x86/out/m5 -no-pie -static build/x86/call_type/inst.o build/x86/call_type/addr.o build/x86/args.o ... ``` So I guess in your case either ``` gcc -o test test.c -I./include -I./util/m5/src -L./util/m5/b

[gem5-users] Re: Why there is miss prediction of non-control instructions

shed. If that's not it, then possibly instructions > like CMOV > (conditional move) that might be (mis)predicted even though they do not > affect control > flow. Not sure if there might be other cases ... > > Eliot Moss > ___ &g

[gem5-users] Re: Page Walker: Where the PTE hits in the memory hierarchy

ield or function/method in the packet that holds this information? > If not, how can I get this information? > > Thanks, -- Best regards, Yuan Yao När du har kontakt med oss på Uppsala universitet med e-post så innebär det att vi behandlar dina personuppgifter. För att läsa mer o