[gem5-users] Cache tag entry query

2012-12-02 Thread Udayan Umapathi
Hello, I am trying to modify the existing Cache model in Gem5. I figured that, \ruby\System\Cache_memory.cc has the definition for the cache memory model. There is a 2d array, "m_cache" of size (cache_number_of_sets*associativity). There is "m_tag_index" hash map o store the tags for the cache

[gem5-users] Ruby model Cache related query

2012-12-03 Thread Udayan Umapathi
Hello All, The query I have is related to the Ruby memory model. I modified the existing Cache memory model(../Ruby/System/CacheMemory.cc). I wanted to know if I have to specify the cache size and associativity and similar parameters throughout command line arguments. The very first assertion

[gem5-users] Help need with cache state transition

2012-12-05 Thread Udayan Umapathi
Hello All, I have successfully modified the gem5 Ruby Cache Memory model suit my needs. At run-time, the benchmark I run terminates due to a invalid state transition. I have a trace of the transitions that I have got through the debug flag "ProtocolTrace". Can somebody give me a clue on how I s

[gem5-users] SLICC L1 Cache

2012-12-08 Thread Udayan Umapathi
Hello All, I am trying to add a custom state to "MESI_CMP_directory-L1cache.sm. I added statement a new cache state similar to , transition(M,L1_Replacement, M_I,){ forward_eviction_to_cpu } for debug purpose. The code does not seem to compile with these changes. Am I doing something wrong?