t.
Best,
Tiago
From: Javed Osmany
Sent: Friday, May 27, 2022 2:53 AM
To: gem5 users mailing list
Cc: Tiago Muck ; Javed Osmany
Subject: CHI compilation error when trying to add L3$ between L2$ and LLC
Hello
So I have simplified the modelling in CHI to
1)
Hi Amin,
You might need to increase the number of outstanding requests in the sequencer
(system.cpu*.data_sequencer.max_outstanding_requests param) and the cache
controllers attached to the sequencer (e.g.: system.cpu*.l1d.number_of_TBEs, if
you have a L2, that need to be adjusted as well).
Yo
Hi Javed,
It seems there is a bug in handling CleanUnique requests. From the code
(src/mem/ruby/protocol/chi/CHI-cache-transitions.sm):
transition({I, SC, UC, SD, UD, RU, RSC, RSD, RUSD, RUSC,
SC_RSC, SD_RSD, SD_RSC, UC_RSC, UC_RU, UD_RU, UD_RSD, UD_RSC},
CleanUnique, BUSY_BLKD) {
Hi,
Thanks Grabriel for responding Jianxing's question!
As the person that made that table, I apologize for any confusion.
If anyone can cast some light on the distinction between ICN and HN that seem
to be used interchangeably in many parts of the spec, you are very welcome :)
At the Protocol/
EM5-1185
This one is still open pending confirmation from the reporter:
https://gem5.atlassian.net/browse/GEM5-1195
Thanks,
Tiago
From: Javed Osmany
Sent: Thursday, September 22, 2022 4:40 PM
To: Bobby Bruce ; The gem5 Users mailing list
Cc: Tiago Muck ; Ja
Hi Shehab,
Your understanding is correct, there are some cases that are not being handled.
This https://gem5-review.googlesource.com/c/public/gem5/+/18414 patched
MOESI_CMP_directory to some extent (there was no cache latency being considered
before) but was not a complete solution. Other then
te latency would
affect each transaction.
Best,
Tiago
From: Shehab Elsayed
Sent: Thursday, May 14, 2020 11:50 AM
To: gem5 users mailing list
Cc: Tiago Muck
Subject: Re: [gem5-users] Question about Ruby cache latencies
Thank you very much for your reply and e
