Re: [gem5-users] DRAMCTRL:Seeing an unusual behaviuor with FR-FCFS scheduler

2014-11-14 Thread Tao Zhang via gem5-users
Prathap, Based on your observation, the activation scheduling seems not doing the best. When data is streamed out from one bank, another bank should be activated in advance (don't need to wait the complete of the current data streaming) to make sure there is no bubbles on the data bus. Can you pri

Re: [gem5-users] DRAM controller write requests merge

2015-01-22 Thread Tao Zhang via gem5-users
Hi Rizwana, see my understanding inline. Thanks, -Tao On Thu, Jan 22, 2015 at 8:12 AM, Rizwana Begum via gem5-users < gem5-users@gem5.org> wrote: > Hello Andreas, > > Thanks for the reply. Sure, I will try to get the patch up on review board. > I have another question: Though this is related to

Re: [gem5-users] DRAM controller write requests merge

2015-01-22 Thread Tao Zhang via gem5-users
The timing of RL (aka tCL) is dedicated to DRAM module. This is the distance from DRAM module receive the CAS command to DRAM module put the first data on the interface/bus. On MC/PHY side, it should account for the signal propagation delay on the command/data bus. In fact, signal "DQS" is also use

Re: [gem5-users] DRAM controller write requests merge

2015-01-22 Thread Tao Zhang via gem5-users
MC I believe should have either it's own clock domain, or might work in L1/L2/Core clock domain. It is more reasonable to assume MC working at the same frequency as DRAM rather than the high CPU clock frequency. In fact, MC frequency is relatively flexible in a real chip. It can run even much

[gem5-users] Re: Segmentation fault in gem5,

2020-10-02 Thread Tao Zhang via gem5-users
Hi Jason, Thanks a lot for posting the code of conduct. Being polite is indeed important and respect should be from both sides. I couldn't see Ciro's avatar in this email thread. However, if you search online, go to his github/stackoverflow profile page, or even browse your own homepage, you wou

Re: [gem5-users] Memory size with DRAMSim2

2014-10-06 Thread Tao Zhang via gem5-users
It depends on what kind of memory you want. You can easily change the row number "NUM_ROWS", column number "NUM_COLS", bank number "NUM_BANKS" to increase the total capacity. I prefer increasing NUM_ROWS since it doesn't change the basic DRAM structure while the other two define a new memory eventu

Re: [gem5-users] DRAM memory access latency

2014-11-04 Thread Tao Zhang via gem5-users
Hi Parthap, the latency tRP+tRCD+tCL+tBURST is only the static access latency for DRAM. In memory subsystem, there is also dynamic queuing delay due to the memory controller scheduling (reordering) and resource availability (bank conflict, refresh, other timing constraints like tFAW, tRRD, tWTR) .