[gem5-users] Dram sim2 running with gem5

Hi , I am new to gem5 , I want to use dramsim2 with gem5 I cloned it and ran scons I am getting error. ClockDoenv.cpp not found Please help me . ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem

[gem5-users] How to simulate RISCV bare metal app in gem5

Hi , i need to access physical memory address directly , i though bare would bypass tlb ie address translation , please help, How to config Gem5 for RISCV baremetal , i found for ARM , but unable to find for RISCV Thnak you Chaitanya .. ___ gem5-user

[gem5-users] How to create riscv mesi 3 level or ruby

Hi I am new to gem5, help in how to create riscv ruby mem model please help me .. Thanks in advance .. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Hi does gem5 Ruby support pthreads lock and unlock

Hi , I am running pthreads matmul program for riscv in se mode , but with lock and unlock instructions I am getting read error in Ruby .. Do i have to compile with mthreads .. Thanks Chaitanya ___ gem5-users mailing list -- gem5-users@gem5.org To unsubsc

[gem5-users] Re: Hi does gem5 Ruby support pthreads lock and unlock

poral deadlocks and > starvation. > > Regards, > > Víctor. > > On 29/6/23 9:03, Srikanta Chaitanya via gem5-users wrote: > > Hi , > > I am running pthreads matmul program for riscv in se mode , but with > > lock and unlock instructions I am getting read er

[gem5-users] Re: Hi does gem5 Ruby support pthreads lock and unlock

. we're looking into it, but haven't been able to track it > down.) > > Cheers, > Jason > > On Thu, Jun 29, 2023 at 4:05 AM Srikanta Chaitanya via gem5-users < > gem5-users@gem5.org> wrote: > >> Thanks for the reply. >> >> On Thu, Jun 29, 2023, 2

[gem5-users] How to collect traces of inorder multicore core simulation

Hi , I want to simulate arm inorder multicore system , first i want to collect trace with simple memory and use trace cpu to simulate my own memory system I tried following tutorial but the trace i am able to get for 03 cpu only, timing simple cpu is not supported While running its giving error A

[gem5-users] How se mode implements system calls for riscv

Hi , I am simulating muticore riscv but when i fork threads it count is less than my spawn count , I just want to read code of system calls , how they are implemented in gem5 Please share me file names Let me know how to identify the system call from elf Please Thanks srikanta _

[gem5-users] Re: How se mode implements system calls for riscv

the syscalls used by a binary. > > As far as multithreading is concerned, I think SE mode is not suitable for > that purpose and you might want to use FS mode of gem5. > > -Ayaz > > On Sun, Jul 16, 2023 at 9:59 PM Srikanta Chaitanya via gem5-users < > gem5-users@gem5.org> w

[gem5-users] How to implement dma in gem5 SE mode

Hi I want to implement dma in gem5 SE mode , I came across gem5 alladin, , how they are able define x86 dma ports , or dcache support dma function ... ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem