Following the procedure in
https://github.com/gem5/gem5/tree/stable/ext/dramsim3#readme , I integrated
DRAMSim3 with the recent Gem5-stable version. But when I execute the following,
./build/X86/gem5.opt configs/example/se.py
--cmd=tests/test-progs/hello/bin/x86/linux/hello --cpu-type=TimingSim
Hi all,
I am trying to bring in another block into the cache in addition to the
requested block whenever there is a miss. I have written the following the code
in the recvTimingReq() in the miss handling part.
PacketPtr NewPacket = nullptr;// Creating a new packet
RequestPtr req = new Request(
Hi Abhishek,
Thanks for the reply. But I want to do this without modifying the prefetcher
part.
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Hi,
You have to add an option 'Level' in cache/Cache.py file so as to differentiate
between different caches. Then you have to goto common/Caches.py and set the
level for all the declared caches. Then in the cache/base.cc declare a variable
and initialize with the Level option. You can start us
Hi all,
I am trying to initiate another request in the cache along with the received
request for a block. The problem is that the translated address for the
requested block with all the checks performed will be given to cache. Now for
the additional request which I want to create, I was trying
Hello Eliot,
Thanks for the reply. Yes, you are right. But even in the case when both the
addresses map to the same page, the entire page might not be allocated for the
process right? It may use only half of the page. Say it has an array of just
1KB(page size - 4KB). Now if the additional reque
I want to check if the address I have generated is valid or not. For that, we
have to access the page table and also perform other checks if there are any.
All the ones which are done while translation. If the page is swapped out, or
if the address is not valid, the request will be dropped.
Thanks. I will try that. How can I add data TLB to the cache? Is it possible
using CacheConfig.py?
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Alright. Thanks a lot Eliot.
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Hi all,
I was trying to pass BaseCache object as a parameter to TimingSimpleCPU. Here's
what I did:
1. In TimingSimpleCPU.py, I have added a parameter name 'cache':
from Cache import BaseCache
cache = (BaseCache(),"Passing cache object")
2. I have declared a pointer for this cache object
Hi all,
To avoid sending the response to CPU in case of a prefetch request, while
giving the response in recvTimingResp(), it will check the target source, if it
is a prefetch it will delete the req and the packet. Now, if a prefetch
request from L1 is a miss in L1 and as well as a miss in L2.
Hi all,
I was trying to add a pseudo instruction(add instruction). I have been
following this tutorial
http://gedare-csphd.blogspot.com/2013/02/add-pseudo-instruction-to-gem5.html
This is with respect to older gem5 versions I guess. Some of the files have
been renamed and I made corresponding ch
Hello Gedare,
Thanks for the reply. I am not sure why I can't see the reply here. Re-building
the gem5 worked. I was busying making changes in many files that I forgot to
rebuild. Now it is working. I have one more question. Can I use a variable
which is present in the cache, here in the pseud
Hi all,
I was trying to use my own debug flag while running in full system mode. I got
an error(Not a valid PC error) while doing it. Initially, I thought there might
be an error in my code. But strangely, the code runs fine if I don't specify my
debug flag. So I was wondering if this because o
Hi Gabe,
Thanks for the reply. I guess prefetcher is varying the output every time. Am I
right?.
Regarding the debug flags, the code works perfectly in SE mode, even in FS mode
if I don't specify any flag it runs fine. The problem comes only if I specify
any flag. If I specify an already exist
Hi all,
I have a few questions regarding SMT in gem5.
1. I tried running SMT in SE mode. The option '--smt' says "Only used if
multiple programs are specified. If true, then the number of threads per CPU is
the same as the number of programs." Does this mean I don't have to set the
no.of hardwa
Hi Jinpeng,
What is the problem that you are facing with --outdir?
-
Saideepak.
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Thanks, Jason.
I should have given the binaries in ' '. When I do that I am getting the error
as mentioned in the link. Are there any other ISAs which do not support SMT as
of know?.
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Hi all,
I am trying to get the PID information from Processinfo: :pid . I got stuck at
the panic which says 'thread info not compiled into kernel'. I have been
looking into older posts regarding this.
https://lists.gem5.org/archives/list/gem5-users@gem5.org/thread/MLWTK3SQMOVZ5IKLVV2L24IVPFA5T
Hi Jinpeng,
I suspect you are giving it in the wrong place. You should specify the option
right after 'build/ISA/gem5.opt' in the command. Hope this helps.
Thanks,
Saideepak.
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Thanks a lot, Ciro. That was very helpful.
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Hi all,
I am unable to build gem5.opt for ALPHA.
Error: Cannot find variables file /home/saideepak/gem5/build/variables/ALPHA or
default file(s) /home/saideepak/gem5/build_opts/ALPHA
Is there any change in the latest gem5? I could see NULL ISA instead of ALPHA
in the build_opts directory and I c
Thanks Abhishek.
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Hi Jason,
How do I run two programs in SMT using FS?
I did that using se.py but I am not sure how to do it in FS mode?
Somewhere I read, it can be done by running both the processes in the
background.
Something like " ./prog1 & and ./prog2 & ".
Do you think that is the correct way? Or is there
Hi all,
I was trying to create a SimObject(named Buffer) and pass it as an argument to
another. I could build the gem5 without errors, but while running, I
encountered the following error:
TypeError: (): incompatible function arguments. The following argument types
are supported:
1. (self:
Hi all,
I can see that the context information is not carried till the LLC. I want the
contextId() to be present at the last level also. Is there any way to maintain
the contextId at LLC?
Any comments are welcome.
Thanks,
Saideepak.
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Hi all,
I came to know that gem5 doesn't support ALPHA anymore. But my question is
about ALPHA in older versions. Did ALPHA support RPCC instruction?
Thanks for your time and any comments are welcome.
Regards,
Saideepak.
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Hi all,
I found that the classic caches in gem5 are either mostly inclusive/mostly
exclusive. I need the cache to be strictly inclusive i.e if a block gets
evicted from L2 that has to be evicted from L1 too. Apart from that, I have
done some of my work in classic caches already.
1. Is it possib
Thank you, Nikos.
I will try both of them.
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Hello Jaspinder,
To run two programs on two different cores in SE mode, use
-c 'prog1;prog2'
-
Saideepak
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Hi all,
How do I run two programs parallelly on two different cores in FS?
Using ' taskset -c 0 ./prog1 && tasket -c 1 ./prog2 ' didn't work. The first
prog worked, but second one gave 'set affinity: invalid argument'.
Similar thing happened with '/sbin/m5 pin 0 ./prog1' and 'sbin/m5 pin 1
./pr
Hi Chandrahas,
Thanks for the reply. But in my case, I cannot launch those programs as
threads( as threads share the same address space), they have to be two separate
programs(with different address space).
-
Saideepak
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You can do that in SE mode by specifying the programs using -c 'prog1;prog2'
and specifying number of cores using -n 2.
But I am still facing the same issue in FS(one program is executed but the
other says invalid argument to sched_affinity).
-
Saideepak
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