Hello everyone,
Could somebody please help me on how to calculate the
miss rate for L1 cache?
I think I should divide "system.l1_cntrl0.cacheMemory_total_misses"
with total accesses to L1 to get the miss rate.
What events do I have to sum to get the total accesses?
Should I sum all L1 events
SI/MESI Protocols.
>
> Take a look here: http://reviews.gem5.org/r/1467/
>
> Malek
>
> On Tue, Oct 30, 2012 at 12:22 PM, Pavlos Maniotis
> wrote:
> > Hello everyone,
> >
> > Could somebody please help me on how to calculate the
> > miss rate f
Hello everyone,
I am looking information about cache memory design/implementation
and its interconnection system with the processor(s). The more
detailed the info the more useful for my needs. (Hardware design,
logic circuits, signals, controller design etc are perfect!)
I imagine all the info I
Hello everyone,
Is there anybody who knows how to calculate miss
ratio using ruby? I think a step by step explanation
would help a lot of us working on gem5.
Thanks in advance,
Pavlos
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-0500, Malek Musleh wrote:
> Hi Pavlos,
>
> I have a patch posted here for this:
>
> http://reviews.gem5.org/r/1467/
>
> I only added support for MESI/MOESI Protocols, but you can extend to
> the other ones also.
>
> Malek
>
> On Tue, Nov 20, 2012 at 11:09
the ruby.stats file.
>
> This is done on a per-cache basis, unless you want sum global
> misses/accesses that accounts for all caches misses/accesses for every
> cache into one value ?
>
> Malek
>
> On Tue, Nov 20, 2012 at 12:29 PM, Pavlos Maniotis
> wrote:
> > Hel
ls/summary of the patch for more information.
>
> Malek
>
> On Tue, Nov 20, 2012 at 1:08 PM, Pavlos Maniotis wrote:
> > Now I understand, thanks a lot. I will try to install
> > the patch and see what results I will get.
> > But it is very strange that such a bug exists in ge
Hello everyone,
I am trying to simulate a system with 4 cpus and
one shared L1 cache (cache shared among cpus).
I tried to modify MESI_CMP_directory.py in
/gem5/configs/ruby by changing this code:
(I actually removed the "for" command and replaced i with 0 -
the idea was to create only one L1 c
On Wed, 2012-11-21 at 12:15 -0600, Nilay Vaish wrote:
> On Wed, 21 Nov 2012, Pavlos Maniotis wrote:
>
> > Hello everyone,
> >
> > I am trying to simulate a system with 4 cpus and
> > one shared L1 cache (cache shared among cpus).
> > I tried to modify MESI_C
Hello everyone,
I use ruby (MOESI_CMP_directory) and I want to simulate a system
with one CPU (frequency=2GHz) and L1 and L2 caches (frequency=4GHz).
I also want the bus between cpu and cache
to run at 4GHz with width 32 bits. So I have to set the cpu
frequency equal to 4GHz (ruby_fs.py -> CPUCla
Pavlos,
>
> There is no bus between the CPU core and the L1, just a "port" connection.
> The PIO bus is only used for PIO, and should not have a great impact on
> your benchmark unless it is very I/O intensive.
>
> Andreas
>
> On 23/11/2012 12:29, "Pavl
CoherentBus between the CPU and L1 if you
> want, but you will have to change the config scripts.
>
> Good luck.
>
> Andreas
>
> On 23/11/2012 14:34, "Pavlos Maniotis" wrote:
>
> >Hi Andreas,
> >
> >Thanks for the info, does it also apply fo
to modify?
I am new to gem5 and I am trying to get familiar with it.
Pavlos
On Fri, 2012-11-23 at 17:06 +, Jack Harvard wrote:
> Why not, just put a bus in between CPUs and L1? But why would you do
> so?
>
> Jack Harvard
>
>
> On Fri, Nov 23, 2012 at 4:06 PM, Pav
Hello everyone,
In ruby_fs.py I try to connect cpu ports and ruby ports through
a coherent bus. I changed these two lines that connect the ports
directly:
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
to this:
cpu.tol1
on init as it
> assumes it is connected to a CPU that does not care. The bus, however,
> does.
>
> Andreas
>
> On 24/11/2012 13:52, "Pavlos Maniotis" wrote:
>
> >Hello everyone,
> >
> >In ruby_fs.py I try to connect cpu ports and ruby ports
egin(); p != slave_ports.end(); ++p) {
> (*p)->sendRangeChange();
> }
>
>
> If it works submit a patch to the review board.
>
> Andreas
>
>
> On 24/11/2012 16:56, "Pavlos Maniotis" wrote:
>
> >What do you think should I do to solve t
t tricky. I don't
> have an easy and general solution. The port would have to know what the
> memory range is.
>
> Andreas
>
> On 24/11/2012 18:10, "Pavlos Maniotis" wrote:
>
> >Thanks Andreas but I got this fatal error:
> >
> >fatal: Unable
sequencer
2) In ruby_fs.py I connected each cpu's cache ports to the one L1 ruby
sequencer created in step 1
In this way I successfully simulated fft splash2 benchmark in ALPHA fs
mode.
Pavlos
On Fri, 2012-11-23 at 19:31 +0200, Pavlos Maniotis wrote:
> I would like to experiment with t
m.ruby._cpu_ruby_ports[0].slave
by this way I connect each cpu's ports to the same sequencer created in
MOESI_CMP_derectory.py and I have used ALPSA ISA.
Pavlos
On Sat, 2012-11-24 at 19:38 -0600, Nilay Vaish wrote:
> On Sun, 25 Nov 2012, Pavlos Maniotis wrote:
>
> > For anyone w
On Sun, 2012-11-25 at 08:29 -0600, Nilay Vaish wrote:
> On Sun, 25 Nov 2012, Pavlos Maniotis wrote:
>
> > In /gem5/configs/ruby/MOESI_CMP_directory.py I changed this code:
> >
> > by this way I connect each cpu's ports to the same sequencer created in
> > MOE
Hi Abusaad,
Check this link: http://www.m5sim.org/Download
Pavlos
On Tue, 2013-01-08 at 02:10 -0800, Abu Saad wrote:
> Hi all
>
>
> how I will able to get latest version of gem5 software
>
>
> regards
> ---
>
> Abusaad
>
> ___
> gem5-user
Hello everyone,
Does anybody know if the default configuration parameters refer to a
specific computer system?
Thanks in advance,
Pavlos
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Hello everyone,
Could you please explain me what exactly is the response_latency in
BaseCache.py and its relationship to the hit latency?
Thanks in advance,
Pavlos
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Hello everyone!
I need a simulator I was wondering if gem5 can do the
job! I want to test how faster would be the execution
time of some benchmarks if I could get faster cache
memories for a given system architecture.
Is it possible in gem5 to make faster the cache models
by changing some para
e plenty knobs related to the
> performance of the memory system, and quite a variety of full-system
> benchmarks that are ready to use.
>
> Andreas
>
>
> On 24/09/2012 10:00, "Pavlos Maniotis" wrote:
>
> >Hello everyone!
> >
> >I need a simul
-0700, Musharaf Hussain wrote:
> Hi, Maniotis Pavlos.
>
> You can do with gem5. At first you should try and see the tutorials
> and slides.
>
> musharaf
>
>
>
> --- On Mon, 9/24/12, Pavlos Maniotis wrote:
>
> From: Pavlos Maniotis
>
Hello every one. I have followed the instructions here:
https://docs.google.com/document/preview?id=1B7nZSqMLwkwoVNEj_58tMPTk4bKWvoEMbokOAjqeC-k&pli=1
and i am trying to run fft benchmark in ALPHA ISA full system mode.
last lines of system.terminal output:
Bridge firewalling registered
802.1
Can somebody help me find where to set cache memory parameters?
For the time I care about Hit & Miss latencies etc...
I use ALPHA ISA in fs mode and I run the splash2 benchmarks
with ruby memory system.
Thanks in advance!
Pavlos
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>
> I think these two files are limited to the classic memory system but
> not Ruby.
>
> Tao
>
> On 10/05/2012 09:29 AM, Anthony Gutierrez wrote:
> > Try looking at the Caches.py and CacheConfig.py files.
> >
> >
> > -Tony
> >
> > On Fr
ase class RubyCache has several
> latency parameters you can use(i.e., dataAccessLatency,
> tagAccessLatency). See its definition in src/mem/ruby/system/Cache.py
> for the detail.
>
> Tao
>
> On 10/05/2012 09:27 AM, Pavlos Maniotis wrote:
> > Can somebody help me find
and miss.
>
>
> Musharaf
>
>
> --- On Fri, 10/5/12, Pavlos Maniotis wrote:
>
> From: Pavlos Maniotis
> Subject: Re: [gem5-users] Cache Hit & Miss latencies
> To: "gem5 users mailing list"
> Date: Friday, Octob
s
> ---
> Musharaf
>
> --- On Sun, 10/7/12, Pavlos Maniotis wrote:
>
> From: Pavlos Maniotis
> Subject: Re: [gem5-users] Cache Hit & Miss latencies
> To: "gem5 users mailing list"
> Date: Sunday
Hello everyone,
Does anybody know when exactly gem5 starts collecting statistics?
I wonder if it includes linux boot process or not.
Thanks in advance,
Pavlos
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Never mind! I just found the answer and is YES, gem5 includes
linux boot in statistics.
Pavlos
On Sat, 2012-10-13 at 02:29 +0300, Pavlos Maniotis wrote:
> Hello everyone,
>
> Does anybody know when exactly gem5 starts collecting statistics?
> I wonder if it includes linux boot pr
Hello everyone,
In /configs/ruby/MI_example.py there is a parameter
named "latency" inside class "Cache(RubyCache)". Is
this value in clock cycles? If yes, does it mean
cycles from ruby clock (src/mem/ruby/system/RubySystem.py)?
Moreover, which components are synchronized with the
above ruby cl
Thank you very much Nilay for your time and
your clear answer!
Pavlos
On Sun, 2012-10-21 at 13:52 -0500, Nilay Vaish wrote:
> On Thu, 18 Oct 2012, Pavlos Maniotis wrote:
>
> > Hello everyone,
> >
> > In /configs/ruby/MI_example.py there is a parameter
> > named
Hello everyone,
I have read the following thread and I feel that I have not completely
understood what is the actual configuration for the CoherentBus (and
generally the Bus) model.
https://www.mail-archive.com/gem5-dev@gem5.org/msg10942.html
Is it just a shared medium between the master and sl
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