I am trying to build M5 with: *scons build/ARM/gem5.opt*
but I am getting the error: Error determining SWIG version. I change swig
2.07 to 2.02 but still the same. I dont have root permisssion but I install
all dependencies on my local directory on Red Hat Enterprise Linux
Workstation release 6.2
variable for determining the version. I’ll fix this.
>
> ** **
>
> Andreas
>
> ** **
>
> ** **
>
> *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] *On
> Behalf Of *Nyunyi Tshibangu
> *Sent:* 20 June 2012 17:58
> *To:* g
sure that you either set SWIG using
> export/setenv etc or specify SWIG = .. on the scons command line.
>
> ** **
>
> Andreas
>
> ** **
>
> *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] *On
> Behalf Of *Nyunyi Tshibangu
> *Sent:* 20 June
ning scons with the same python version you're
> linking with.
>
> You can also look through the mailing list archives for other situations
> where people have had this same _Py_ZeroStruct problem.
>
> Steve
>
>
> On Thu, Jun 21, 2012 at 2:14 PM, Nyunyi Tshibangu wro
Hello,
I am trying to run spec2000 in SE mode using ARM simulator but I am getting
error just trying to compile the benchmark.
here is the errror message:
ece% ../build/ARM/gem5.opt ./mytest_gzip.py
..
File "", line 1, in
File "/local/home/nmtshiba/M5/gem5/src/python/m5/main.py", line 359
Hello,
I am trying to run spec2000 in SE mode using ARM simulator but I am getting
error just trying to compile the benchmark.
here is the errror message:
ece% ../build/ARM/gem5.opt ./mytest_gzip.py
..
File "", line 1, in
File "/local/home/nmtshiba/M5/gem5/src/python/m5/main.py", line 359
naries/arm/linux/gzip not
found
I replaced '/dist/m5/cpu2000' in cpu2000.py with my own local directory
'/local/nmtshiba/M5/gem5/cpu2000'
On Fri, Jun 29, 2012 at 3:25 PM, Ali Saidi wrote:
> **
>
> ARM and linux need to be passed as strings and they need to be lower
ed to be lower case.
>
> Ali
>
>
>
>
>
> On 29.06.2012 15:16, Nyunyi Tshibangu wrote:
>
>
> Hello,
> I am trying to run spec2000 in SE mode using ARM simulator but I am
> getting error just trying to compile the benchmark.
> here is the errror message:
>
Hi,
I am trying to simulate my personal code written in C++ with gem5
I started just by compiling "hello.c" that came with gem5 and use it
instead of using the pre-compiled binary"hello". here is what I get:
build/X86/gem5.opt configs/example/se.py -c ../c_code/my_hello
fatal: Object file is
gt; On Sat, Jun 30, 2012 at 7:16 PM, Nyunyi Tshibangu wrote:
>
>> Hi,
>> I am trying to simulate my personal code written in C++ with gem5
>> I started just by compiling "hello.c" that came with gem5 and use it
>> instead of using the pre-compiled binary"
ini > <mailto:amin...@gmail.com>> wrote:
>>
>>This should help:
>>
>> http://comments.gmane.org/**gmane.comp.emulators.m5.users/**10990<http://comments.gmane.org/gmane.comp.emulators.m5.users/10990>
>>
>>Amin
>>
>>On Sat, J
I am running a simple hello world in SE mode and realized that the number
of cycle given by system.cpu.numCycles is the the same for the
configuration without cache, does this make any sense? normally I would
expect number of cycle to be lower if cache is used. is there anythign
wrong? or am I look
I am having hardtime understanding the number of cycles from SE mode
statistcs
1)running with L1 only
build/X86/gem5.opt configs/example/se.py --cpu-type="detailed" --caches
--maxinsts=1000 --cmd=bzip2/bzip2 --options="bzip2/input.program"
I am getting number of cycles as: system.cpu.numCycl
e L1 i cache and there
> is very little re-use on the data side. Removing the L2 probably lowers the
> access time to main memory by a substantial amount which improve
> performance.
>
>
>
> Ali
>
>
>
> On 02.07.2012 20:06, Nyunyi Tshibangu wrote:
>
> I am ha
I m reading through past discussion about this issue and trying to use
recommended fixes but no chance. I increase stack size in process.cc as Ali
and others suggest up to 256*1024*1024 but I am stuck with this error. this
happen for X86 as well as ALPHA for all my cpu2006 benchmarks. it would
stay
yes including all other benchmarks
On Wed, Jul 4, 2012 at 2:08 AM, Mahmood Naderan wrote:
> Hi
> Do you run bzip2?
>
> // Naderan *Mahmood;
>
>
>
> On Wed, Jul 4, 2012 at 10:34 AM, Nyunyi Tshibangu wrote:
>
>> I m reading through past discussion about this issue
l 4, 2012 at 2:13 AM, Mahmood Naderan wrote:
> With all spec2k6?!!
> Which changeset are you using?
>
> // Naderan *Mahmood;
>
>
>
>
> On Wed, Jul 4, 2012 at 10:40 AM, Nyunyi Tshibangu wrote:
>
>> yes including all other benchmarks
>>
>>
>> On We
> have you edit
> rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
>
> in sim/syscall_emul.hh?
>
> // Naderan *Mahmood;
>
>
>
>
> On Wed, Jul 4, 2012 at 10:49 AM, Nyunyi Tshibangu wrote:
>
>> yes, I tried bzip2, gcc, milc. for isntance I am running g
, Mahmood Naderan wrote:
> Just a suggestion...
>
> have you edit
> rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
>
> in sim/syscall_emul.hh?
>
> // Naderan *Mahmood;
>
>
>
>
> On Wed, Jul 4, 2012 at 10:49 AM, Nyunyi Tshibangu wrote:
>
>> yes, I
I really need some help. I cant attach my config.ini or any other
attachment because it's rejected. anybody?
command:
build/X86/gem5.opt --outdir=m5out/x86/500Minst_512MB_200ns_bzip2_program
--stats-file=stats_L1_L2_default.txt --dump-config=config_L1_L2_default.ini
configs/example/se.py --maxinst
I am running the following command with ruby but it looks like it's
ignoring my cache configuration. no info on L2 in given in config.ini or
statistics. any idea how to use ruby with benchmark?
build/X86/gem5.opt --outdir=m5out/ruby configs/example/se.py --ruby
--cpu-type="detailed" --caches --l2
never mind, I was not using a proper protocol...
On Sun, Jul 8, 2012 at 9:47 PM, Nyunyi Tshibangu wrote:
> I am running the following command with ruby but it looks like it's
> ignoring my cache configuration. no info on L2 in given in config.ini or
> statistics. any idea how to
does anybody have a MI_example ruby protocol that implement separate
L1icache and L1dcache? is it possible to modify MI_example.py to implement
this? the code only implement a combined I/D cache
thanks
Marcus
___
gem5-users mailing list
gem5-users@gem5.
I saw the following answer in FAQ: "In SE mode, simply create a system with
multiple CPUs and assign a different workload object to each CPU's workload
parameter. If you're using the O3 model, you can also assign a vector of
workload objects to one CPU, in which case the CPU will run all of the
wor
; I'm not sure exactly what you want? Do you want multiple workloads with or
> without smt? In either case you're probably going to have to modify
> configs/example/se.py a bit to suite your use case.
>
>
>
> Ali
>
>
>
>
>
>
>
> On 24.08.2012 21:07
25 matches
Mail list logo
