Hi everyone,
Does anyone know the backup links for the GEM5 101 links as they are down?
I cannot seem to access all of them
thanks
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Hi everyone,
I am trying to connect a SPM(Scratchpad memory) (SPM is derived from the
class SimpleMemory) to my gem5 configuration, where the spm is at almost
the same level as the cache. But when I try to read or write to it, it
gives an error that the memory address is not found. I have tried nu
Hi everyone,
I have made a system that includes a scratchpad memory(using the class
Simple Memory as SPM) at the same level as a level 2 cache. The problem
that am facing is that I can read and write to it in increments of 8 rather
than 4 for type int, i.e. Pointer++ gives wrong value at an addres
Hi again everyone,
It would be really nice if someone could assist me as I've tried almost
everything and I cannot figure it out.
Thanks
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Hi Bobby,
In my workload, am simply calling pointer++ once, but I do not know how it
automatically increments as if I am calling pointer++ twice,
here is an example of a very simple version of my workload which also
provides the incorrect address reading
int main()
{
// spm address starts fr
Hi everyone,
I have been following this tutorial(
http://www.m5sim.org/wiki/images/b/b2/Tsinghua%27s_Presentation_for_gem5_Workshop_2012.pdf)
to integrate GEM5 to the eclipse debugger but I am not able to do it, maybe
because the tutorial is quite old.
It would be really helpful if someone could
Hi Boris,
I am referring to the guest code, I can't just seem to configure GEM5 as a
"remote target" in debug configuration as you have mentioned. It would be
nice if you could list the steps.
Thanks again,
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Hi everyone,
Is there a way where I can set a checkpoint and print the tick number when
gem5 has reached that checkpoint. What I would like to do is get the number
of ticks a certain function has taken to run. Do m5ops have this capability
or i have to use some other method.
Any help would be app
rpns() as well
>> if you don't care to implement your own pseudo instruction.
>>
>> So I guess for your purposes, record the ticks at the beginning and end
>> of your function.
>>
>> Best,
>>
>> Dan
>>
>> On Thu, Aug 6, 2020 at
Hi everyone,
I have been modifying the MinorCPU to be like an out of order CPU for
certain memory instructions. My modification involved this "instructions"
to not stall the pipeline and allow the cpu to continue processing other
instructions.
Coming to the problem that I am facing is that when i
Hi everyone,
Is it possible to send more than one memory request from the dcacheport to
the memory system without stalling the pipeline. What i have seen so far is
that when one memory instruction is send to the memory, then another memory
request cannot be send to the memory as sendTimingReq ret
to be put below (closer to memory) a
> "point-of-coherence" crossbar. Also, I believe that by default that
> crossbar is on 16 bytes wide, so a single cache line request could take 4
> cycles, which might be why the CPU is blocking?
>
> Cheers,
> Jason
>
> On S
27;re probably going to be seeing some errors in your memory. The
>> non-coherent crossbar was designed to be put below (closer to memory) a
>> "point-of-coherence" crossbar. Also, I believe that by default that
>> crossbar is on 16 bytes wide, so a single cache line request cou
cpu->getPort().sendFunctional(newPkt)
> ----------
> *From:* Muhammad Aamir via gem5-users
> *Sent:* Tuesday, August 18, 2020 1:04 PM
> *To:* Jason Lowe-Power ; gem5 users mailing list <
> gem5-users@gem5.org>
> *Cc:* Muhammad Aamir
> *Su
Hi everyone,
As the title suggests, is it possible to send for a request from the CPU
asking for data in the memory without looking into the caches? If yes, how
can it be done.
Also is it advisable to create another port like the dcacheport, and
connect that port directly to the memory bus? i.e.
Hi everyone,
i am trying to add an additional CPU port to the MinorCPU, which is similar
to a dcacheport, i have tried to implement it and i have gone to a point to
also edit the BaseCPU, so it can accept the new port, but when building
GEM5 I get the following errors, Would someone explain to me
Hi everyone,
I have created a new cpu port which accesses the main memory and bypassing
the caches when reading from memory. When I try to read from the main
memory via this port, I sometimes fail to read it and it is read as a 0.
This only happens when I try to read a value almost after updating
Hi everyone,
I have noticed that when I am using pseudo-instructions such as:
m5_reset_stats(0,0), m5_dump_stats(0,0) and m5_rpns() i get a less number
of simulated ticks compared to when I don't use them.
Am particularly interested in m5_rpns() as I am measuring the time taken by
a certain funct
Hi everyone,
I am running the pagerank algorithm that is provided by the GAP Benchmark,
and it is well known that pagerank has very bad cache utilization. But
when I run the code in GEM5 on one level of cache i get a very low
missrate, i.e. approximately 1% and it goes to a maximum of 3% for a gr
Hi everyone,
I have noticed that the stat: "system.cpu.dcache.overall_miss_rate::total"
is the same if I only use 1 level of cache or use the system with a level
2 cache. As we know it should change but it remains exactly the same, how
is this possible? Would someone be kind enough to explain why
> On Thu, Oct 22, 2020 at 1:01 PM Muhammad Aamir via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi everyone,
>>
>> I have noticed that the stat:
>> "system.cpu.dcache.overall_miss_rate::total" is the same if I only use 1
>> level of cache
uhammad Aamir via gem5-users wrote:
> > Hi, the miss rates are exactly the same when using the in-order CPU for
> both when using level 1
> > cache alone and using it with level 1 and 2 cache. For O3CPU, there is a
> very minor difference (i.e.
> > a difference of 0.01) but a
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