Hi AIl
I am digging GEM5 'src' and trying to understand the execution flow, but
didn't get it completely yet.
My aim is to define a new level of cache hierarchy between L1 & L2 with
MESI portocol.
Just wanted to know, is defining transitions
in MESI_CMP_directory-L1cache.sm
& MESI_CMP_directory-L2
Hi all
Is GEM5 Cycle accurate? or their is some internal adjustment.
because whatever simulation I do, ticks always results in multiple of
Thousand.
eg @ tick 304265000, @ tick 302535000
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>
> I hope that explains it.
>
> Andreas
>
> From: Mann Mann mailto:evebu...@gmail.com>>
> Reply-To: gem5 users mailing list gem5-users@gem5.org>>
> Date: Monday, 24 September 2012 23:24
> To: gem5-users mailto:gem5-users@gem5.org>>
> Subject: [gem5-us
Hi All
I am working on GEM5 for my project.
objective is to explore various Cache Architectures on multiprocessor
systems.
My aim to add a Cache layer on MESI protocol, I have gone through GEM5
source number of times,
but couldnt identify where to start. I mean what files to be modified.
Regards
Hi All
in Shared Multiprocessor Simulation, I understood that simulator assigns
sequencer to each process, but I need to grab exact flow,
I want to understand how shared variables are used, and how data flow
between these processors.
(In detail : How virtual/physical page mapping is maintained in s
at 5:29 PM, Nilay Vaish wrote:
> On Fri, 5 Oct 2012, Mann Mann wrote:
>
> Hi All
>> in Shared Multiprocessor Simulation, I understood that simulator assigns
>> sequencer to each process, but I need to grab exact flow,
>> I want to understand how shared variables are
e between L1 & L2
>>This is one way to go. You can also have two or more levels with in the
same .sm file.
Can you please explain a bit, how to implement/go about two levels in same
.sm file?
Warm Regards'
Mann
On Sat, Oct 27, 2012 at 12:59 AM, Nilay Vaish wrote:
> O
