[gem5-users] Negative value for system.mem_ctrls_1.actEnergy

Dears, I run most recent version of gem5 without any modification to source code and with following command in SE mode: ./build/ALPHA/gem5.opt ./configs/example/cmp.py -b lbm,lbm,lbm,lbm,lbm,lbm,lbm,lbm --mem-type=DDR4_2400_x64 --mem-size=16GB -n 8 --caches --l2cache --cpu-type=detailed --l2_si

Re: [gem5-users] Negative value for system.mem_ctrls_1.actEnergy

s there is a typo > somewhere, or even an inconsistency in the actual data sheet. > > > > Second it would be good to know if you're doing any form of check > pointing. If so there could be something not getting reset properly. > > > > Andreas > > > > --

Re: [gem5-users] panic: Running multiple instances of Gem5 in parallel

You should add m5.disableAllListeners() at the end of of your simulation python script for example at the end of fs.py or se.py but before Simulation.run(.. m5.disableAllListeners() root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass) On Wed, Mar 18

Re: [gem5-users] panic: Running multiple instances of Gem5 inparallel

llListeners() Simulation.setWorkCountOptions(test_sys, options) Simulation.run(options, root, test_sys, FutureClass) > > > - 원본 메일 - > > *보낸사람*: Majid Jalili > *받는사람* : gem5 users mailing list > *날짜*: 2015년 3월 18일 수요일, 17시 30분 46초 +0900 > *제목*: Re: [gem5-u

[gem5-users] Range of Address in a Large Memory System

Hi, I run gem5 in SE mode with following command for SPEC CPU 2006 workloads. ./build/ALPHA/gem5.opt ./configs/example/cmp.py -b libq,libq,libq,libq,libq,libq,libq,libq --mem-size=16GB --mem-type=simple_mem -n 8 --caches --l2cache --cpu-type=atomic --cpu-clock=4GHz --l2_size=4MB --cacheline_siz

[gem5-users] M5ops for KVM

Hi, I am trying to annotate my benchmark with m5ops and use KVM to expedite the simulation. However, when I am trying to use the address-based APIs such as m5_switch_cpu_addr, I am getting the following link error: /usr/bin/ld: ../../util/m5/build/x86/out/libm5.a(m5op_addr.o): relocation R_X86_64

[gem5-users] Simulation halts after calling pseudo instructions

Hi, In my code, I am calling m5_switch_cpu to trigger cpu change. However, as soon as it is called my simulation process goes to the S state, and is put to sleep. Here is my code: #include #include "gem5/m5ops.h" using namespace std; int main() { cout<<"Hi"<

[gem5-users] Time resolution in FS mode

Hi, In Tailbench, the function clock_gettime is called to associate timestamps to each request ( Tailbench request not gem5 memory request) in order to calculate P95 at the end of the simulation. The problem I am facing is that this function does not provide a high resolution, so I have many reques

[gem5-users] Top-down micro arch analysis

Hi, Has anyone developed some script to do top down microarchitecture analysis with gem5 stats? https://www.intel.com/content/www/us/en/develop/documentation/vtune-cookbook/top/methodologies/top-down-microarchitecture-analysis-method.html ___ gem5-users

[gem5-users] Gem5 Simpoints speed

Hi, I used Valgrind (200 million interval) to generate the BBV files of SPEC CPU 2017. Then, using SimPoint, I created the weights and intervals. For example for 641.leela, I got Intervals8589 0493 16196 22850 3 Weights:0.332078 00.10355 10.403174 20.161198 3 Now, I need to run gem5 to create the

[gem5-users] Changing configuration after taking the Simpoints

Is Changing the configuration (e.g. LLC size, latency, mem-type) after taking Simpoints valid? For example, if I take my points for LLC size of 2MB, would it be correct to increase the LLC size to 4MB and increase the latency later on or I have to retake the simpoints with the newer configuratio

[gem5-users] reading script in newer kernels

I followed the instructions at  http://www.lowepower.com/jason/setting-up-gem5-full-system.html to create a newer disk image. However, I am not using the gem5.service due to some technical difficulties. I manged autologin and I can run any script right after login. The problem is when I run /sbi

[gem5-users] Different stats when taking checkpoint with atmoic and KVM

I took two separate checkpoints with atomic and KVM CPUs. Now, when I restore from checkpoint, I get completely different results. The numbers of KVM-taken checkpoint seems to be wrong. For example, the number of cycles for a particular benchmark for 1 billion instructions is around 100B cycles

[gem5-users] Error while running the latest version of gem5 fs mode/atomic cpu

Hi, I just cloned the latest version of gem5 and tried to run it in FS mode. However, if I set the cpu type to atomic I get the following error: gem5.opt: build/X86/cpu/simple/atomic.cc:544: virtual Fault AtomicSimpleCPU::writeMem(uint8_t*, unsigned int, Addr, Request::Flags, uint64_t*, const st

Re: [gem5-users] Error while running the latest version of gem5 fs mode/atomic cpu

By reverting the commit "cpu,mem: Add support for partial loads/stores and wide mem. accesses" I solved the issue. But still not clear to me how it helped.  On Monday, May 20, 2019, 1:28:31 PM CDT, Majid Jalili wrote: Hi, I just cloned the latest version of gem5 and tried

[gem5-users] Restoring KVM-taken SimPoints

The simpoints taken for SPEC CPU 17 are far from the beginning. So, in order to be able to take simpoint in a reasonable time frame, I am using the KVM CPU:1) Boot with KVM and taking a checkpoint2) Running the application with simpoints information as input with KVM CPU and taking the simpoints

Re: [gem5-users] TLB translate time and miss delay

Any update? On Friday, August 25, 2017, 4:40:30 AM CDT, 李莉 wrote: hello all， How can I get the TLB miss delay in fs x86 mode? Does gem5 simulate the TLB translate time ,i read the source code about x86/tlb.cc ,pagetableWalker.cc ,but i can't find the information about the time .does

[gem5-users] latest version of gem5 and FS mode issue

Hi, I tried the latest version of gem5 in the FS mode with two disk images: gem5 website and my own disk image. However, I am getting the following error, if I enable --cpu-type=DerivO3CPU (for other cpu types it is just fine) gem5.opt: build/X86/mem/packet.hh:1094: T* Packet::getPtr() [with T =

[gem5-users] System-wide pointer

Hi, Is there any way to have a system-wide pointer in gem5? For example, what if for some reasons I need to have access to LLC prefetcher from pipeline? I can do tc->getCpuPtr()->getPort("dcache_port", 0).getPeer().majidAddrLength(tc, arg1, arg1, arg2); Also, I am aware of Probe Monitors, but still

[gem5-users] virtual address support for prefetchers

When I enable the use_virtual_addresses ans start feeding the prefetchers with VA address, I see no translation happening, and I ended up with situation where all new addresses are dropped because the reference to tlb is null. Any help is appreciated. use_virtual_addresses = Param.Bool(True,

Re: [gem5-users] virtual address support for prefetchers

(system.cpu[i].dtb) This will link the dcache prefetcher with the data TLB. Hope this helps, Javier. On Fri, Oct 25, 2019 at 4:56 PM Majid Jalili wrote: > When I enable the use_virtual_addresses ans start feeding the prefetchers > with VA address, I see no translation happening, and I ended u

[gem5-users] How to suspend a packet in cache

Hi, What is the best way to suspend a packet in the cache. Let's say for a read access to L2, I have to suspend the request until another request comes in, although the main request might be a hit in L2. One solution might be checking the secondary request in inpuSidePort::recvTimingReq(PacketPt

[gem5-users] Stream benchmark mismatch stats

I am running a simple stream benchmark that does a simple addition: m5_reset_stats(0,0); for(int i = 0 ; i ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Stream benchmark mismatch stats

Let me correct myself. If I set the Size to 5K, then there would be total of 10K loads (for a[i] and b[i]), so i expect to see 10K/8=1250. On Thu, Feb 20, 2020 at 11:45 AM Majid Jalili wrote: > I am running a simple stream benchmark that does a simple addition: > m5_reset_stats(0,0);

Re: [gem5-users] Stream benchmark mismatch stats

jid, > > Are you taking into account the instruction fetches? > > Cheers, > Jason > > On Thu, Feb 20, 2020 at 9:53 AM Majid Jalili wrote: > >> Let me correct myself. If I set the Size to 5K, then there would be total >> of 10K loads (for a[i] and b[i]), so i expe

[gem5-users] Simpoint with (Ruby, MOESI Hammer, X86, multicore-KVM)

Hi, I am trying to take simpoints for a X86 multicore machine. I compiled version 21.0.1 for X86_MOESI_Hammer protocol, and applied KVM patches. Now, I can boot up and see all the cores online. However, when I pass --take-simpoint-checkpoint arguments with simpoint files and intervals, what happen

[gem5-users] Re: Simpoint with (Ruby, MOESI Hammer, X86, multicore-KVM)

Can someone explain the trick behind "RubySystem::memWriteback()" function? More specifically, why all events first dequeued from ruby's queue and then simulation invoked with the current tick, and fianlly all events are written back to the queue? On Fri, Jun 11, 2021 at 1:08

[gem5-users] The puzzle of multicore simulation in gem5

Hi, I hope you read this email entirely. I have been working with gem5, for now, more than a few years. However, I am still struggling with multicore simulation, although I have found single-core simulation very convenient with gem5. This is particularly weird given lots of new features are being

[gem5-users] Enabling L1 and L2 prefetchers in Ruby

Has anyone attempted to enable L2 and L1 prefetchers for Ruby? I have seen the L0 prefetcher, but could not find L1 and L2's. I am trying to add such a feature, but I found the L1 and L2's state machines more complicated than L0's. Do you have any advises? Majid ___

[gem5-users] Re: Enabling L1 and L2 prefetchers in Ruby

Thanks for the reply! I'm using MESI_Threee_Level. I checked both develop and stable branches. Based n what I see, only one prefetcher is created at this line https://github.com/gem5/gem5/blob/eb919229e63c4daa208a1d9e4856755c1e914154/configs/ruby/MESI_Three_Level.py#L129 Also, by looking at the st

[gem5-users] Re: Enabling L1 and L2 prefetchers in Ruby

Thanks, that's great! I just have a follow-up question: Can we have CHI for X86? I compiled gem5 for X86_CHI, and it was compiled successfully. However, I was wondering if it would be working correctly in terms of functionality and for longer runs? On Fri, Jul 16, 2021 at 10:26 AM Gabriel Busnot v

[gem5-users] 4-core ARM with fs.py and fs_bigLITTLE.py

Hi, I am using the following commands for the fs.py and fs_bigLITTLE.py: ./build/ARM/gem5.opt ./configs/example/fs.py --caches --mem-size=64GB --kernel /home/cc/disks/binaries/vmlinux.arm64 --disk /home/cc/disks/disks/ubuntu-18.04-arm64-docker_big.img -n 4 --machine-type VExpress_GEM5_V1 ./build

[gem5-users] Re: 4-core ARM with fs.py and fs_bigLITTLE.py

ld you > try to rebuild the bootloader in system/arm/bootloader/arm64 and make sure > the config script is pointing to it? > (Either with M5_PATH or by using the --bootloader option) > > Please let me know if this works > > Kind Regards > > Giacomo > > > -Or

[gem5-users] Re: Performance tanking with memory intensive benchmark compared to real machine

Matching up performance with that of a real machine is extremely difficult. I have been trying this and usually cannot come very close. However, you can find my advice below: 1) Use prefetchers, at least one per level. They can make a huge difference! For example, for predictable access patterns (e

[gem5-users] Snoop Directory Size

Hi, The default value for the snoop directory is 8MiB. I am trying to find the minimum size for my configuration. I ran a dual-core system (-n 2) with 2 levels of caches with one L1D prefetcher (DCPT), with small L1 and L2 caches: build/X86/gem5.fast ./configs/example/se.py --caches --l2cache -n

[gem5-users] Conditional DPRINTF

Hi, Is there any way or trick to make a debug flag conditional? For example, --Debug-flags=Cache if pkt->getAddr()==0xABCD Thanks! ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_ur

[gem5-users] Writing checkpoint fails

Hi, I am trying to take simpoint for some SPEC 17 applications, using the command below in fs mode: sudo build/X86/gem5.opt -d lbm_checkpoint ./configs/example/fs.py --caches --l2cache -n 1 --disk-image /home/cc/disks/disks/linux-x86.spec.img --kernel /home/cc/disks/binaries/vmlinux-4.19.83 --t

[gem5-users] Segfault with -F

Hi, I compiled the latest stable version of gem5 and tested the Hello World: build/X86/gem5.opt ./configs/example/se.py --caches --l2cache -n 1 -c tests/test-progs/hello/bin/x86/linux/hello --cpu-type=DerivO3CPU However, as soon as I enable the -F flag to fast-forward with the atomic CPU, I get

[gem5-users] Re: Writing checkpoint fails

This is the commit breaking the simulation: https://github.com/gem5/gem5/commit/d0b7de0f870d22f7d271ad0c698567b24d38fe80 I am still trying to figure out what needs to be fixed. Any help would be appreciated! On Tue, Feb 15, 2022 at 1:59 PM Majid Jalili wrote: > Hi, > > I am tryin

[gem5-users] Re: Writing checkpoint fails

ce >> Room 3050, >> Kemper Hall, UC Davis >> Davis, >> CA, 95616 >> >> web: https://www.bobbybruce.net >> >> >> On Thu, Feb 17, 2022 at 11:52 AM Majid Jalili via gem5-users < >> gem5-users@gem5.org> wrote: >> >>> This i

[gem5-users] Compilation time

Hi, I feel compiling gem5 is taking longer than what it should take for me. I was wondering if anyone can measure and report for this scenario: [a routine scenario happens when we debug]: Compile gem5. Then touch one cc file, and then recompile with the command below: time scons build/X86/gem5.o

[gem5-users] Re: Compilation time

With lld, it is way faster! I'm done to 25 seconds. Thanks! [I did not get your email Gabriel in my inbox to reply to] On Wed, Mar 23, 2022 at 10:35 PM Majid Jalili wrote: > Hi, > > I feel compiling gem5 is taking longer than what it should take for me. I > was wondering if a

[gem5-users] Re: Low memory bandwidth achieved with STREAM benchmark

Hi, Make sure your system has enough MSHRs, out of the box, L1, and L2 are set to have a few MSHR entries. Also, stride prefetcher is not the best, you may try something better: DCPT gives me better numbers. On Fri, Apr 15, 2022 at 4:57 AM Zicong Wang via gem5-users < gem5-users@gem5.org> wrote:

[gem5-users] Re: Low memory bandwidth achieved with STREAM benchmark

gt; read and write combined (Ratio) > - > > It’s indeed improving the achieved bandwidth, but still a little far away > from the peak bandwidth of DDR3_1600 (12800 MiB/s). stats.txt is uploaded > for reference ( > https://gi

[gem5-users] Re: Low memory bandwidth achieved with STREAM benchmark

78999ee46..6d921bb2b 100644 --- a/src/cpu/o3/lsq.cc +++ b/src/cpu/o3/lsq.cc @@ -115,6 +115,8 @@ LSQ::LSQ(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams ¶ms) thread[tid].init(cpu, iew_ptr, params, this, tid); thread[tid].setDcachePort(&dcachePort); } + +std::cout<<"ma

[gem5-users] Difference between Directory and Snoop filter

Hi, Can someone help me to understand the difference between the snoop filter and the directory? They are very similar in terms of functionality, but I do not understand the differences. Majid ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscr

[gem5-users] Converting KVM-taken checkpoint to atomic-needed checkpoint

Hi, Is it practically possible to convert the KVM-taken checkpoint such that I can restore it with Atomic CPU? This is particularly important because I have to use KVM to take my checkpoints on an ARM machine and then transfer them to my X86 cluster to run the checkpoints. I cannot avoid KVM on AR

[gem5-users] Long linkage

Hi, Why does the recent version of gem5 takes very long on the last step when creating the gem5.opt? My 2-month old repo is just fine, but the new version takes a very long to finish link. I tried on three different machines with the different OS but no improvement.

[gem5-users] ARM and opening a file

Hi, When I was running SPEC CPU 2017, in particular 505.mcf_r, I noticed that if gem5 should open a file, it will not make any progress. I dig into mcf code and found when the read_min function is called the simulation freezes. Then I started running a simple benchmark as follows, that just prints

[gem5-users] Re: Converting KVM-taken checkpoint to atomic-needed checkpoint

> Davis, > CA, 95616 > > web: https://www.bobbybruce.net > > > On Fri, Apr 9, 2021 at 2:29 PM Majid Jalili via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi, >> >> Is it practically possible to convert the KVM-taken checkpoint such that >> I c

[gem5-users] Re: Converting KVM-taken checkpoint to atomic-needed checkpoint

a file), which seems doable for a microbenchmark, but > maybe not for a large workload. > > Arthur > On 4/15/21 5:18 AM, Majid Jalili via gem5-users wrote: > > I have tried this option, the problem is for a simple microbenchmark, if I > do not use KVM, the IPCs make no sense. I

[gem5-users] device_irq_level

Has anyone faced the following error when compiling gem5 on an ARM host? error: 'struct kvm_sync_regs' has no member named 'device_irq_level ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(w

[gem5-users] checkpoint_aggregator.py for arm

Hi, checkpoint_aggregator.py works on X86 checkpoints, has anyone converted it to work with ARM checkpoints ? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s