[gem5-users] Coherence protocols and interconnection network

Hello, I was trying to figure out the MESI_CMP_directory cache coherence protocol in gem5. From what I understand the directory system is based on a point to point interconnection network -- does that mean that there is not a bus at all to communicate on between caches/memory? For example, if

[gem5-users] mmap failure during simulation

Hello, I'm trying to run an application which uses mmap. It runs fine on my native x86 machine. However when I run it on gem5 it seems mmap is failing: REAL SIMULATION info: Entering event queue @ 0. Starting simulation... warn: instruction 'fnstcw_Mw' unimplemented warn: instruction

[gem5-users] Testing cache coherence protocols

Hello all, I'm attempting to modify the MESI_CMP_directory cache coherence protocol. I was wondering if there is an easy way to write some simple memory operations and and view the resulting way the state machine and network respond, other than inspecting the output of --debug-flags=RubySlicc (

[gem5-users] SLICC/transition question

Hello, I had a question about the transition function in SLICC. The documentation shows an example "transition(IM, Data, M)" and says that "The initial state is IM. If an event of type Data occurs in that state, then final state would be M." Then there is another example with sets: "transition(

[gem5-users] Interactions between memory system and instructions

Hello, I'm attempting to make some modifications to the Ruby memory system and the MESI directory protocol. I was wondering if anyone could give me an overview of what happens when for example a load occurs -- how the system interacts to check/update MESI protocol states, looks at what is curre

[gem5-users] gem5 port error

Hello, I'm trying to run some full system ruby simulations with multiple cores. I can start the simulation with 2 cores, but I've tried 4 and 8 and I get the attached error message. I've looked this issue up a little bit and it seems that this should only be happening when messing with the port

[gem5-users] Ruby L2 cache latency

Hello, I'm doing simulations with the Ruby memory system. I found a comment in configs/ruby/MESI_CMP_directory.py that says: "# Note: the L2 Cache latency is not currently used" Does this mean that the ruby memory system for MESI_CMP_directory is not timing accurate when going to the L2? What

[gem5-users] Ruby L2 Cache Latency

Hello, I'm doing simulations with the Ruby memory system. I found a comment in configs/ruby/MESI_CMP_directory.py that says: "# Note: the L2 Cache latency is not currently used" Is this comment old/no longer true? Or is the ruby memory system for MESI_CMP_directory not actually timing accurate

[gem5-users] Multiple CPUs not recognized by program

Hello, I'm booting into full system mode with 4 processors and running a test program which calls: sysconf(_SC_NPROCESSORS_ONLN); to determine the number of CPUs on the machine. However the return value is 1 when run on gem5. I'm starting gem5 with the following parameters: ./build/X86/gem5.

[gem5-users] meta data for static/dynamic insts

Hello all, I'm looking to load in meta data for instructions in the O3 arm CPU. I was thinking that instead of adding to the binary, this would be easiest to accomplish by having a meta data file which associates each static instruction's address with its meta data. Then when instantiating stat

[gem5-users] Segfault when changing renameWidth

Hello, I believe I have found a bug in the O3 cpu model. I have simply adjusted the renameWidth from 8 to 16 in src/cpu/o3/O3CPU.py. Doing this causes the commit unit to seg fault at line 1286 in src/cpu/o3/commit_impl.hh. It appears the fromRename buffer size is incorrect (value of 55356032).