Re: [gem5-users] [gem5-dev] Creating new SimObject error

Hi Mohamed, The gem5-users list is probably a better place to ask this question (forwarding it there). It's not totally clear from your email what "CLASSONE" is, though I appreciate all of the detail :). However, the error that you're seeing is because you didn't set the variable named "system.c

Re: [gem5-users] SSE Instructions in Gem5

To directly answer your question: The labeling of instruction in gem5 is not accurate at all. Feel free to fix the labeling and submit a patch to reviews.gem5.org, though! We'd welcome the fixes. BTW, you're correct that SIMD instructions are labeled as floating point instructions. I've noticed th

Re: [gem5-users] Gem5-Ruby component-Cache coherence protocol simulation

Hello, I think there may be a couple of mistakes in your command line: "./build/ARM/gem5.opt configs/example/se.py --ruby --cpu-type timing -c testa/test-progs/hello/bin/X86/linux/hello" First, it looks like you've build gem5 with support for the ARM ISA, but you're trying to run an X86 binary. I

Re: [gem5-users] Gem5-Ruby component

That error is saying the file " tests/test-progs/hello/bin/X86/linux/hello" doesn't exist. I think you need a lowercase X86 (x86). Jason On Thu, Jun 23, 2016 at 6:04 AM <206115...@nitt.edu> wrote: > > Hi > > > ./build/X86/gem5.opt configs/example/se.py --ruby --cpu-type=timing -c > tests/test-pr

Re: [gem5-users] scp between gem5 simulated linux system and real linux system

Hi Liyang, You're correct that you can't use scp because gem5 doesn't have an ethernet connection to the outside world. What we usually do to get data onto the disk images is mount the disk image on the host machine and make modifications, then boot the disk image with gem5. You can use the pytho

Re: [gem5-users] cache coherence protocol using ruby memory model

See http://qa.gem5.org/140/scons-2-0-10-and-swig-with-python-2-7-5-on-gem5. I believe this is a problem with your swig version. See also http://gem5.org/Dependencies. Cheers, Jason On Mon, Jun 27, 2016 at 4:41 AM <206115...@nitt.edu> wrote: > > Hi everyone, > > I want to simulate MESI cache cohe

Re: [gem5-users] SSE Instructions in Gem5

son. I'll try to fix it and possibly submit a patch. >> >> >> >> On Wed, Jun 22, 2016 at 9:30 AM, Jason Lowe-Power >> wrote: >> >>> To directly answer your question: The labeling of instruction in gem5 is >>> not accurate at all. Feel fre

Re: [gem5-users] Enable Printing in Linux 4.3

Hello, These are not printed to stdout in full system mode, but are saved in the terminal file (something like system.pc.com_1.terminal). You can also see the terminal output if you telnet into the guest system (e.g., using m5term in gem5/util/term). Cheers, Jason On Thu, Jun 30, 2016 at 4:48 AM

Re: [gem5-users] Restoring from the checkpoint created by hack_back_ckpt.rcS

Hi Azadeh, I'm not certain what the problem is. However, you don't have to use the O3 CPU to "restore-with". That option is the CPU that is used during checkpoint restore, not the CPU used once checkpoint restore is complete on the main simulation. To choose which CPU to use for the main simulatio

Re: [gem5-users] Enable Printing in Linux 4.3

pe this helps. Jason On Thu, Jun 30, 2016 at 10:44 AM Vanchinathan Venkataramani < dcsv...@gmail.com> wrote: > Hi Jason > > I cannot see the output in system.terminal file. I am using the latest > gem5 version. > > Best regards > V Vanchinathan > > On Thu, Jun 3

Re: [gem5-users] Operation Classes in Arm

Or even better, post the patch on reviewboard (http://reviews.gem5.org) so we can incorporate your work! Cheers, Jason On Sat, Jul 9, 2016, 8:08 PM Ayaz Akram wrote: > Hi Fernando, > > Will it be possible for you to post the relevant code here ? That will > just save some of my time. > > Thank

Re: [gem5-users] Cache warmup with ruby

Hello, All you have to do is exit the simulation after 500 million instructions and then reset the stats. You can exit the simulation after a certain number of instructions easily (see what the -I option does). Then, you simply call m5.stats.reset() from Python to reset the stats. Then, you can c

Re: [gem5-users] GEM5 SPARC SE mode O3 CPU - no TLB info

Hello Monir, You're correct that in SE mode the TLB is never accessed. You'll have to use FS mode if you want to use a TLB model. If you want to dump periodic stats, you can use a method similar to how the Simulation.py script takes periodic checkpoints. You can put "m5.simulate(period)" in a loo

Re: [gem5-users] Making a C application work on multiple cores with gem5

Hello, If you're using full system mode (FS mode), you can use pthreads or any other threading library just like on a real machine. If you're using syscall emulation (SE) mode, then you can use the m5threads library which is a pthreads-like library (http://repo.gem5.org/m5threads/). If I've misun

Re: [gem5-users] Physmem in SE Mode

Hi Monir, The AbstractMemory class (along with the System class) implements the physical memory of the system. When configuring gem5, if you instantiate a memory object (e.g., DRAMCtrl like DDR3_1600_x64) this object will register the physical memory with the System object. The with the DRAMCtrl,

Re: [gem5-users] Physmem in SE Mode (Jason Lowe-Power)

(anoir nechi) >2. Making a C application work on multiple cores with gem5 > (anoir nechi) >3. Virtual to Physical Address in ARMv8 FS Classic Memory > (Vanchinathan Venkataramani) > 4. Re: Making a C application work on multiple cores with >

Re: [gem5-users] Physmem in SE Mode

Hi Monir, The protocol is only used if you are using the Ruby memory model (e.g., --ruby option). Otherwise, the memory system is the classic memory model. Classic uses something like "MOESI" coherence, but it's not modeled in as much detail as Ruby's coherence protocols. I'm not sure why you're

Re: [gem5-users] Adding a new GPU model

Hi Sebastian, You can also check out gem5-gpu https://gem5-gpu.cs.wisc.edu/wiki/ as another example of how to integrate a GPU model into gem5. Feel free to send us questions on gem5-gpu-dev@googlegroups. Cheers, Jason On Tue, Aug 9, 2016 at 2:31 AM Andreas Hansson wrote: > Hi Sebastian, > > Th

Re: [gem5-users] Physmem in SE Mode

Hi Monir, It still seems like the MinorCPU just isn't compiled in. I don't have time right now to try it myself to see how to do it. Another thing you can do to check to see if the MinorCPU is compiled is to look at the generated files in build/.../cpu. These files are in the same directory struct

Re: [gem5-users] Physmem in SE Mode

Yes, I would try deleting the entire build (build/, not just build/SPARC) directory and recompiling from scratch. I'm not familiar with the details of the T1's coherence protocol. If you really care about modeling the coherence protocol, then you should be using the Ruby memory model. You can look

Re: [gem5-users] Physmem in SE Mode

@Andreas, I agree with what you said. I didn't word my previous email very carefully. I meant, that if you want to model the *specific coherence protocol* of the T1, then you probably want to use Ruby (and would likely need to write a new protocol). @Monir: Sounds like you got it working finally!

Re: [gem5-users] real run-time of the benchmark

sim_seconds is the time in the simulated system. host_seconds is the time on the host. You want to use sim_seconds for the performance of simulated applications. Jason On Mon, Aug 15, 2016, 8:03 AM leila zamani wrote: > There are "sim_seconds" & "host_seconds" in the stat file of GEM5, which >

Re: [gem5-users] Physmem in SE Mode

Hi Monir, I really don't know much about the internal workings of the MinorCPU model (or really any of them). If you can track the problem down to something specific, and still can't figure out the solution, I'd suggest posting a new thread here on the users list. Cheers, Jason On Fri, Aug 12, 2

Re: [gem5-users] Use m5ops "m5_dumpreset_stats()" In SE mode

Hi Anouar, It looks like you're getting a linking error. Make sure that you either include the appropriate assembler (.S) file in your compiling step, or assemble the .S file and link the appropriate object (.o) file. Cheers, Jason On Sun, Aug 14, 2016 at 11:36 AM anoir nechi wrote: > Hi > > i

Re: [gem5-users] ARM big.LITTLE

Hi Felipe, I'm not super familiar with the ARM model (and these weird dtb files), but I believe the rcS file that the simulator is looking for is actually on the host. This somewhat describes how FS simualation works: http://gem5.org/Running_gem5#Basic_Operation. The rcS file is a script which is

Re: [gem5-users] FW: Gem5-Ruby_HBM_Parsec_Deadlock

Hi George, The system you're simulating is quite a stress test for the Ruby protocol you're using! What protocol have you compiled? The problem you're running into could be very simple. It's possible that due to the high bandwidth of the system, some of the queues in Ruby are filling up and causi

Re: [gem5-users] FW: Gem5-Ruby_HBM_Parsec_Deadlock

Hi George, I was only saying that your system with 8 HBM controllers is much more bandwidth than the original developers of Ruby imagined. Therefore, I wouldn't be surprised if you are encountering some bugs that others have never seen. MESI_two_level is one of the more tested protocols, so I wou

Re: [gem5-users] The latest version of x86 Linux kernel

Hi Jasmin, 12.04 is pretty ancient too, it's over 4 years old now! Either way, from what I hear, it's pretty easy to compile your own kernel and get it to run on gem5, for both x86 and for ARM. However, I don't have any direct experience. I expect you would probably need to modify the config file

Re: [gem5-users] creating multiple socket system

Hi Wei, If you're using Ruby, you probably just need to configure the network topology to match a dual-socket system. In fact, most of the topologies were originally written with multi-socket systems in mind. Check out configs/topologies/*. You may also need to modify the coherence protocol somew

Re: [gem5-users] Set DRAM Latency when using it with O3_ARM_v7a.py

Hi Anouar, I believe your problem is that you are not using the O3_ARM_v7aRAM object as the DRAM controller for your system. If you want to use your new class in the system that you instantiate, you have to instantiate this new class. I believe that for se.py, the memory controllers are created vi

Re: [gem5-users] Stuck at "initiateAcc not defined!"

Hello, Try running the script that ships with current gem5 (not gem5-stable). You can find up-to-date learning gem5 scripts in configs/learning_gem5. Cheers, Jason On Wed, Aug 31, 2016 at 8:09 AM Oscar Rosell wrote: > Could you send the contents of simple.py file? > > Thanks, > > Oscar Rosell

Re: [gem5-users] Rebuilding after changing config files

Hi all, Just to be totally clear: Re-compiling gem5 is *only required if you modify something in src/*. No changes to any files in configs/ require compiling gem5 again. (Note: even if you modify .py files in src/ you have to recompile.) The only other time that a compile is required is if you ch

Re: [gem5-users] SPARC_SE -> Unimplemented Instruction

Hi Monir, I won't belabor the point about using a better supported ISA this time :). For your other options, I definitely wouldn't change the instruction to a warning. That may be appropriate for a few instructions, like prefetch, but it's inappropriate for most. I don't know the SPARC ISA off the

Re: [gem5-users] Minor Cpu x86

Hi Ayaz, This sounds like a bug to me. You should post your fix on reviewboard ( http://reviews.gem5.org/) so we can incorporate it into the mainline gem5. Thanks! Jason On Tue, Sep 6, 2016 at 2:00 PM Ayaz Akram wrote: > I'll appreciate if someone who has used x86 minor cpu can look into outpu

Re: [gem5-users] SPARC_SE -> Unimplemented Instruction

Hi Monir, No, I don't have any good suggestions for you. Too bad you're not inside ARM. I bet they have something internally ;) (note: I have no knowledge of what ARM may or may not be doing internally). Another (semi-)sarcastic response: It may be less effort to add the RISC-V ISA to gem5 than t

Re: [gem5-users] Running full system with SMT

Hi Ferran, First, for SMT support, I believe it is implemented in the O3 CPU, and you should be able to enable it by updating your CPU configuration (numThreads, see src/cpu/BaseCPU.py). However, as far as I know, SMT is not tested in our regression tests, so it's possible (likely) that there are

Re: [gem5-users] RISC-V ISA

Hi Alex, This is very exciting. I think I was just telling somebody a day or two ago that RISC-V would be great to have in gem5! For the submission process see http://gem5.org/Submitting_Contributions. Also, you should be sure to follow the coding style: http://gem5.org/Coding_Style. In the same

Re: [gem5-users] arm_detailed error

Hi Anouar, You're seeing this error because the script configs/common/CpuConfig.py isn't importing your script correctly, or something. See line 138 in the aforementioned file. I would bet there is an error in your file causing it to throw an exception when it is imported. You can remove the try

Re: [gem5-users] ARM config error

Hi Anouar, I'm not sure what's going wrong. I would run gem5.debug in a debugger and trace back where the stat is being defined that is causing the error. It's likely that you didn't instantiate some object that some other object expects. Note: the simple scripts in the Learning gem5 book were bu

Re: [gem5-users] RISC-V ISA

his, please cite "RISC5: Implementing the > RISC-V ISA in GEM5," which we plan to submit soon. > > Thanks, > Alec Roelke > > On Fri, Sep 9, 2016 at 10:07 AM, Jason Lowe-Power > wrote: > >> Hi Alex, >> >> This is very exciting. I think I was just tel

Re: [gem5-users] Running ad hoc workload

Hi Jasmin, I'm not sure if I totally understand what you're trying to do, but I think I can give some pointers in the right direction. First, to "control gem5" you can use any python script that you create. There is a python API, and in fact, that's what all of the scripts in configs/examples use

Re: [gem5-users] RISC-V ISA

Hi Monir, You should just download the patches off of reviewboard and test them. Having someone else use them will be a great way to increase the test coverage. If you have any issues while you're using them post the issues to reviewboard. For the timeline to get something accepted... it's hard t

Re: [gem5-users] Custom memory mapping

Hi Seshan, I'm not sure if I totally follow what you're trying to do, but I'll do my best to give you some relevant information. In gem5, there is an AddrRange class. You can set each cache (or memory controller, or any slave port) to respond to some specific set of AddrRanges. Thus, if you wante

Re: [gem5-users] gem5-users Digest, Vol 123, Issue 2

Yes, please don't use gem5-stable. gem5-stable is just an arbitrarily old version of the gem5 development repository. We are currently discussing the best way forward for gem5-stable, and it looks like we're going to just remove it. Cheers, Jason On Thu, Oct 6, 2016 at 3:53 PM Monobrata Debnath

Re: [gem5-users] Problem with workload

Hi Anouar, You should create 4 different Process instances each with the hello command. Cheers, Jason On Thu, Oct 6, 2016 at 5:20 PM anoir nechi wrote: > > > *Hi* > > *I succeeded to make a four core ARM system based on the se.py file ... > the only problem i have now is that when i assign fou

Re: [gem5-users] New Pseudo Instruction for Clearing a Cache Status Bit

Hi Farzad, Are you using the classic caches or Ruby? If you're using the classic caches, I'm not sure I can help much. You'll have to somehow get a pointer to all of the cache objects and then do some kind of magic to clear the bits. If you're using Ruby, you can easily add a function to RubySys

[gem5-users] Removing the gem5-stable repository

Hi All, We're planning on removing the gem5-stable repository from the gem5 repo next week. If you have an objection to this, please let us know in the next few days. Some context: Most recently, gem5-stable was just a branch of the development repository (gem5) that was tagged quarterly. gem5-st

Re: [gem5-users] Problem with workload

, in > main > exec filecode in scope > File "ARM _A9/ARM_A9_Config.py", line 67, in > process[i] = LiveProcess() > NameError: name 'process' is not defined > *My code is logically right what could be the problem.* > > > On Fri, O

Re: [gem5-users] Assigning multiple workloads

This should work. Attached is a diff for the simple.py script in configs/learning_gem5/part1/ that has 4 CPUs and runs hello 4 times. Hopefully this helps. For a multithreaded application, I believe you'll use a similar config script (instantiate multiple processes all with the same binary file p

Re: [gem5-users] Fwd: warn:unimplemented function 13 and hack: Assuming logical destinations are 1 << id. warn: Address 0x100000000 is outside of physical memory, stopping fetch

Hi Bhargavi, I doubt changing the CPUID is the right thing to do. Have you tried running the same workload and kernel with the atomic CPU (and classic memory system)? Do you get the same error? I'd start there. Also, don't use gem5-stable, use repo.gem5.org/gem5. We are removing gem5-stable very

Re: [gem5-users] Streamcluster x86 FS mode segfault

HI Zamshed, Can you give more information? Is gem5 crashing or is the application running on the guest? Where is the segfault occuring? Have you tried using gdb to track down the problem? If you're using gem5-stable, you should update to gem5 (repo.gem5.org/gem5). That may just fix the problem.

Re: [gem5-users] Restore from checkpoint and disable cores

Hi Ardash, I'm not sure if it ever makes sense to disable a core coming out of a checkpoint. What would happen to all of the architectural state of that core? Would the process that's running on the core just die? I haven't ever tried this, but you may be able to emulate this by using the "switch

Re: [gem5-users] Streamcluster x86 FS mode segfault

streamcluster_static 1 3 1 5 5 3 none > /parsec/install/inputs/blackscholes/out_stream_all.txt 2 > echo "Done :D" > /sbin/m5 exit > /sbin/m5 exit > > I tried gem5, but it didn't work. I am wondering what could be the > problem. > > Regards. > > On Fri,

Re: [gem5-users] Reconfiguring the X86 during run time

Hello, I don't believe there is a way to dynamically change these things "out-of-the-box". However, it's certainly possible to accomplish these things with changes to gem5's code. Each of those configuration options would likely require different changes. One thing gem5 *does support* is changing

Re: [gem5-users] Understanding of stats.txt of the parsec-alpha benchmarks simulation

Hi Mengyu, A new region of the stats.txt file is added every time "m5.stats.dump()". So, if you trace through the python config file that you're executing (configs/custom/fs_elastic.py), you should be able to find where all of the places are that this function is called. Without going through the

Re: [gem5-users] L3 in Classical Model

Hi Tanmay, An example banked L3 can be found on my github page: https://github.com/powerjg/gem5/blob/devel/simplefs/configs/myconfigs/system/caches.py The interconnection networks in configs/topologies only apply to the Ruby memory model, not the classic caches. If you're working on something tha

Re: [gem5-users] Segmentation fault when adding CheckerCPU

Hi Anouar, I've never tried to use the checker CPU myself, so I can't tell you exactly what's wrong. Have you used gdb to find out where the error is occuring? I assume it's a null pointer dereference. So what object isn't allocated that should be? Jason On Fri, Oct 21, 2016 at 10:16 AM anoir ne

Re: [gem5-users] Create separate L2 cache for each CPU

Hi Anoir, You can also look at this script: https://github.com/powerjg/gem5/blob/devel/simplefs/configs/myconfigs/system/caches.py It should be very simple to do what you're suggesting. You just need to create the cache and crossbar objects and hook them up. Pretty much any topology you can think

Re: [gem5-users] KVM: Unknown error when starting vCPU (hw reason: 0x80000021)

Hi Zehan, This is a relatively common error. In fact, even on systems where kvm works, I sometimes get this error. You may want to try applying the following patch from reviewboard. http://reviews.gem5.org/r/2613 Hopefully that solves the problem. If not, you can try this patch, from Nilay Vaish

Re: [gem5-users] Assigning multiple workloads

gt; *Please take a look at the test_lock code * > > > On Wed, Oct 12, 2016 at 4:42 PM, anoir nechi wrote: > > Thank you Jason > > On Wed, Oct 12, 2016 at 4:39 PM, Jason Lowe-Power > wrote: > > This should work. > > Attached is a diff for the simple.py script

Re: [gem5-users] possible deadlock detected, running X86 FS mode with ruby

Hi Bhargavi, This error means that there may be a deadlock in the coherence protocol. As Michael said in reply to your other email, using the ProtocolTrace debug flag is a good place to start. I would start the trace around the time the request that detects the deadlock is issued (--debug-start=16

Re: [gem5-users] Running Error

Hello, It should be "system.cpu.interrupts*[0]*.pio = system.membus.master" The part that needs to be changed is bolded, underlined, and italicized. See configs/learning_gem5/part1/simple.py for the complete script. Jason On Sat, Oct 29, 2016 at 12:06 AM Muhammed Emin Öztürk < muhammedemi...@gma

Re: [gem5-users] Understanding of cache trace of ALPHA timing CPU

In addition to what Rodrigo says, if you want to model a cache coherent memory system in detail, you should be using the Ruby memory system, no the classic caches. Ruby performs all coherence actions in detailed timing mode. Also, for an in order CPU, you may want to try out the MinorCPU. It works

Re: [gem5-users] Simulating multiprogrammed & multithreaded workloads in SE mode?

Hi Majid, Yes. This is possible. To run multiple different processes, you can create multiple CPUs with multiple "LiveProcess" objects. For multi-threaded applications, I believe you need to have enough CPUs create (enough hardware contexts) and then link to m5threads instead of the pthreads libra

Re: [gem5-users] Understanding of cache trace of ALPHA timing CPU

Hello, To reply to a post, you should just click "reply" in your email client. For your question... I would look at the code that is executed with the Exec debug flag. By reading the code you should be able to step through and figure out what's going on. Jason On Thu, Nov 17, 2016 at 4:12 PM me

Re: [gem5-users] gem5 smt in SE mode

Hi Antonis, SMT support is not very robust in gem5 right now. It would not be surprising at all if there were bugs. I would bet you're running into some bug that hasn't been found before. I'm not very familiar with the O3 code, so I'm sorry to say I don't know what the problem may be. Hopefully s

Re: [gem5-users] uncacheable addresses

Hi Lorenzo, Are you trying to use [0x1-0xF] as PIO? If so, this example might help you figure out how to do what you want. https://github.com/powerjg/gem5/commit/86394e326cede3be7b26eb728dd6a9a0a93406bf It's for x86, but it contains an example of how to use PIO in SE mode to communicate f

Re: [gem5-users] simulate a racetrack memory in gem5

Hi Simon, As far as I know there aren't any racetrack memory models for gem5. Depending on what you're trying to implement with racetrack memory (e.g., cache or main-memory) there are a number of examples of similar things in the codebase. The DRAM controller is a really good example of how to ma

Re: [gem5-users] Mesh Topology with Ruby Coherence Protocols

Hi Azin, I believe the mesh (and mesh-dir-corners) topologies make some assumptions about the order that the cache controllers are created in. I'm not sure exactly what's going wrong, but I would add some print statements in the topology config file and see what order the different nodes are creat

Re: [gem5-users] Problem with I/O mapping in SE mode

Hi Lorenzo, This specific problem is that the variable "workload" is a Python list). The line probably should be the following. root.system.cpu.workload[0].map(0x,0x,256) Jason On Wed, Nov 16, 2016 at 5:58 PM Lorenzo Zuolo wrote: > Hi, > > I'm trying to instantiate a fake_isa i

Re: [gem5-users] Simulating multiprogrammed & multithreaded workloads in SE mode?

ing "for i in xrange(np):" with > "for i in xrange(len(multiprocesses)):", but it throws an error > ​ which I believe means I should somehow assign a workload to all CPUs​ > : > > ​ > === > fatal: Must specify at least one workload! >

Re: [gem5-users] gem5 with systemC example

Hi Evan, It looks like the TrafficGen object was not built into your gem5 binary. Make sure you have protobuf installed, as it is required for the traffic generator (see src/cpu/testers/traffic_gen/SConscript). When you run scons, you should see a line that looks like Checking for GOOGLE_PROTOBUF

Re: [gem5-users] simulate a racetrack memory in gem5

d gem5 is OK, but > when I rum a test, I got a segment fault. I use gdb to trace, and find out > it happened in "blkSize(p->system->cacheLineSize()", and the value of the > p->system > is 0x0. So it seems that the parameter isn't . But I do set it in the >

Re: [gem5-users] Running Brillo/Weave on Gem5?

Interesting question, Lunkai! I'm unaware of anyone trying to do this. However, since Brillo is Linux/Android-based it should be possible to get it working. You may want to start by looking at the Android support for ARM in gem5. This may help get you going. From taking a quick look at it, it seem

[gem5-users] Learning gem5 Tutorial in conjunction with HPCA 2017

e. More information can be found on the website for Learning gem5 ( http://learning.gem5.org). Feel free to email me any questions ( ja...@lowepower.com). Hope to see you in Austin! Cheers, Jason -- Jason Lowe-Power PhD Student University of Wisconsin-Madison, Department of Computer Science

Re: [gem5-users] Cache enabling

Hi Pranshu, Are you using a timing CPU model (TimingSimpleCPU, MinorCPU, or DerivO3CPU)? Also, you should read the python config file code carefully and make sure that it is generating the system you are expecting (e.g., when you don't have caches enable there actually aren't any caches). You can

Re: [gem5-users] Cache enabling

a > B.E(Hons) Electrical and Electronics > Birla Institute of Technology and Science, Pilani > Ph : +91 7597634875 <+91%2075976%2034875> > > > On Mon, Dec 5, 2016 at 8:18 PM, Jason Lowe-Power > wrote: > > Hi Pranshu, > > Are you using a timing CPU model (TimingS

Re: [gem5-users] Cache enabling

7597634875 <+91%2075976%2034875> > > > On Tue, Dec 6, 2016 at 8:44 PM, Jason Lowe-Power > wrote: > > Hi Pranshu, > > m5out/config.ini is the file you want to look at. Or, as Andreas suggests, > you can look at m5out/config.dot.pdf if you have pydot instal

Re: [gem5-users] Manipulation data in Cache with Gem5

Hi Emin, You can start by looking at the cache code in src/mem/cache. It should be pretty obvious where the data is stored (e.g., see line 77 in cache.hh). If you wanted to randomly corrupt some data, you could add a new event that fires at a random interval and chooses a block to corrupt, as an e

Re: [gem5-users] Does "Status Matrix" page reflect the current status?

Hi Majid, The status matrix is quite out of date. I would take everything it says with a grain of salt. x86 works pretty well in SE mode with any of the CPU models. There are a few corner cases where there are bugs, but it's good enough that many people have been using it to publish papers for ye

Re: [gem5-users] Does "Status Matrix" page reflect the current status?

st dev branch and > se.py config file to create 4*4 mesh in case of ruby and 16 CPUs with > crossbar in case of classic memory model. > > So, is classic memory system + x86 + multithreading + SE a combination > that is expected to work reliably? > > Thanks, > Majid > > O

Re: [gem5-users] Does "Status Matrix" page reflect the current status?

suggest to not mention the various Ruby protocols > to just say “Classic” and “Ruby”. Any objections? > > Andreas > > From: gem5-users on behalf of Jason > Lowe-Power > Reply-To: gem5 users mailing list > Date: Wednesday, 14 December 2016 at 15:25 > To: gem5 users mailing

Re: [gem5-users] get read/write cache data of gem5

Hello, You may want to take a look at the memory probes (e.g., the files in src/mem/probes). With these, you can get a trace off all of the read and write data. Jason On Wed, Dec 14, 2016 at 9:40 PM 没名字 <13630583...@163.com> wrote: > Hi , I am new to gem5 . And I am using gem5 to get the data

Re: [gem5-users] m5thread fatal error

Hi Mahesh, The problem is exactly what the fatal says: the sys_clone syscall implementation assumes there is one thread context per process. You need to either modify this implementation to understand your coprocessor or add a thread context for the coprocessor in the config script. See createThr

Re: [gem5-users] User functions

Hi Jasmin, I've never done what you're trying to do, but I have a couple of ideas. First, does your binary have all of the debug symbols? If not, that could help. Second, you may need to just take the addresses generated by gem5 (e.g., during a call) and correlate them to the addresses in your bi

[gem5-users] gem5 Governance

Hello gem5 community, First, I would like to thank all of our users. You are "the most important members of the community and without them the project would have no purpose." A while ago (June 2015), I started the process of codifying the governance of our community ( http://thread.gmane.org/gman

Re: [gem5-users] m5thread fatal error

ank you in advance! > > Mahesh > On Thu, Dec 15, 2016 at 12:55 PM, Jason Lowe-Power > wrote: > > Hi Mahesh, > > The problem is exactly what the fatal says: the sys_clone syscall > implementation assumes there is one thread context per process. You need to > either modif

Re: [gem5-users] Monitoring access towards different cache line during execution time

Hello, You can add a CommMonitor to your memory hierarchy where ever you want to intercept memory requests (e.g., between the CPU and the dcache for all data cache accesses). Then, you can create a MemTraceProbe. This will create a trace file as specified by you in the params when instantiating th

Re: [gem5-users] 答复: 答复: Monitoring access towards different cache line during execution time

m5 itself can confirm with me for such data, as I have already > do the calculation/analysis very highlevelly. > > > Is it possible to do so..? Sorry I am a software engineering people, and > my question/concern would be very unreasonable... If it is not possible, > just let me know

Re: [gem5-users] Setting the parameters of ARM O3 model

Hello, I just tested this. I changed line 68 of configs/common/O3_ARM_v7a.py and then ran diff between the old an new config.ini files and line 567 changed. Modifying those classes should have the desired effects. Cheers, Jason On Sat, Dec 24, 2016 at 1:54 PM Morteza RezaAliPour < rezaalipour.k.

Re: [gem5-users] Setting clock and latency for SimpleMemory model

You should change the parameter in the config scripts, not the source files. You many have to make some modifications to the main config file (fs.py in your case) to get the desired result. Jason On Sat, Dec 24, 2016 at 8:04 AM Morteza RezaAliPour < rezaalipour.k...@gmail.com> wrote: > Hi > > I'

Re: [gem5-users] Understanding the memory address in the trace

Hello, I believe your confusion is because the addressed in the binary are virtual addresses, but the address trace shows physical addresses. You may be able to modify the address trace code to print both the virtual and physical addresses (when the virtual is available). IIRC, you can use pkt->re

Re: [gem5-users] Speedup the x86 full system simulation under monitoring

Hi Shuai, Are you looking for the data that is in guest address 0x5891e1? If so, I would create a new Request and Packet object and use the then send a functional request to the memory system. The AbstractMemory object that represents the main-memory of the guest (e.g., DDR3_1600... or whatever me

Re: [gem5-users] trace cpu for full system dual mode

Hi Mohammad, I can't see why that wouldn't work. Though others have much more knowledge about dual mode. Almost certainly you're going to have to write your own config scripts or heavily modify the current ones to simulate such a system, though. Let us know if you run into any issues. I'd be inte

Re: [gem5-users] Monitor and dump the cache state during full system simulation

Hi Shuai, There is currently nothing built into gem5 to dump the cache state (unless you're using Ruby in which case you can look at the code to take a checkpoint in the RubySystem class and the CacheTrace class). However, it should be pretty simple to dump the data in the classic caches. You woul

Re: [gem5-users] When will gem5v become available in gem5 mainline?

Hi Chao, You may want to contact the authors directly to see if they have plans to try to integrate their code into the mainline. As far as I know, there are not any patches from the authors on reviewboard. You may want to search through the patches on reviewboard, though, and see if you find anyt

Re: [gem5-users] Spec CPU2006 416.hmmer Error: addr already mapped

Hi Agustin, Is it possible that you're running out of memory on the guest? What is the expected memory footprint of hmmer? It could also be that the required stack space is larger than gem5 expects. To help track this problem down, I would start by running with the debug flags "SyscallBase" or "S

Re: [gem5-users] Thread binding to cores in FS mode simulation of ALPHA ISA

Hello, The pthread affinity functions should work correctly in FS mode. You can also use numactl, if it's installed on your disk image to bind things to a specific CPU. I don't think there's any other simple way. Since you're using full system mode, the OS gets to choose what process is running on

[gem5-users] Reminder: Learning gem5 tutorial early registration deadline Jan 6

ation can be found on the website for Learning gem5 ( http://learning.gem5.org). Feel free to email me any questions ( ja...@lowepower.com). Hope to see you in Austin! Cheers, Jason -- Jason Lowe-Power PhD Student University of Wisconsin-Madison, Department of Computer Sciences http:/

Re: [gem5-users] Understanding the memory address in the trace

nitor.master = system.cpu.dcache.cpu_side > > > Sincerely, > > -- > *发件人:* Jason Lowe-Power > *发送时间:* 2017年1月2日 7:51:45 > *收件人:* ps4 lover; gem5-users@gem5.org > *主题:* Re: Understanding the memory address in the trace > > Hello, > >

  1   2   3   4   5   6   7   8   >