[gem5-users] Clear stats after x instructions without switching CPU

Hi All, There are a number of similar threads on this list, but I haven't found one that answers my particular question. What I'd like to do is: -simulate for x insts -clear stats -simulate for y insts with same CPU --fast-forward is closest to what I'm trying to do, but it switches between

Re: [gem5-users] How Gem5 achieve cycle accurate

The idea isn't much different from an RTL simulation. In an RTL sim, time is advanced by a step, all the flops are updated to their new values, time is advanced by another step, etc. gem5 does the same thing with processor structures--for every time step, structures get updated. There are two k

Re: [gem5-users] Is it Information

It means that the smallest unit of time gem5 understands is 1picosecond (1ps = 1s/1). -Erik On 05/12/12 05:45, M.S wrote: When ever I want compile my Program said : Global frequency set at 10 what's it mean? ___ gem5-users m

Re: [gem5-users] Running multiple instances of gem5 on a cluster?

I haven't had any trouble doing what you describe, but I tend to run in SE mode (no .IMGs or kernels). What are the error's you're getting? -Erik On 31/01/13 00:22, Gabriel Yessin wrote: Should there be any problem with running a large number of instances of gem5 out of the same gem5/ folder (

Re: [gem5-users] problem while running the same binary file in different frequencies for ARM platform

Hi Negar, clock and cycles are what you would expect to see in hardware: If your clock (period) is set to 1000 (picoseconds), then you're running at 1GHz, and will see 1 billion cycles every second. A tick is an artificial simulator construct that represents the smallest unit of time that the

Re: [gem5-users] problem while running the same binary file in different frequencies for ARM platform

I got from different frequencies, again for one application? (I attached the trend if you want to have a look) Sorry if I asked lots of questions, and thank you again for your help and attention. Cheers Negar On 2/21/2013 6:33 PM, Erik Tomusk wrote: Hi Negar, clock and cycles are what you would expec

Re: [gem5-users] problem while running the same binary file in different frequencies for ARM platform

instructions. The three other stats are for one benchmark running on one cpu core with 3 different frequencies. Now, if these outputs are correct and meaningful, I'd really appreciate it if you tell me what should I calculate as an accurate comparison parameter for different frequencies.

Re: [gem5-users] problem while running the same binary file in different frequencies for ARM platform

but varies when running other frequencies in between. Cheers Negar On 26/02/13 17:23, Erik Tomusk wrote: Hi Negar, For the experiment you describe, what is the behavior of system.cpu.numCycles? If you draw a graph with numCycles, does it look like the graph with sim_ticks? -Erik On 25/02/

[gem5-users] Classic cache aliasing and hashing

Hello All, Does the classic memory model do any sort of address hashing or other similar magic when storing data in the L1D cache? I've been running a very simple microbenchmark with varying sizes of the L1D cache and data set (in SE mode). For a very small number of combinations of data set

Re: [gem5-users] Classic cache aliasing and hashing

ik, It doesn't, but memory allocation is pretty dump in SE mode. VA -> PA, so it's certainly possible you're getting into a case where lots of things conflict. Ali On 12.03.2013 16:27, Erik Tomusk wrote: Hello All, Does the classic memory model do any sort of address ha

Re: [gem5-users] Classic cache aliasing and hashing

thological case. Thanks for the help. -Erik On 13/03/13 13:41, Ali Saidi wrote: Hi Erik, You can use the debug-flag CacheRepl and see what is getting replaced and when. Ali On 13.03.2013 11:09, Erik Tomusk wrote: Hi Ali. I don't think just a direct mapping from virtual to physic

Re: [gem5-users] Relationship between period size and power

Hi Shervin, This probably isn't the best place to ask about McPAT, but then again there aren't any good places to ask about McPAT. In McPAT, power (P) is a function of energy (E) and time (T): P=E/T . Energy is a function of processor activity (A): E=f(A). Therefore: P=f(A)/T. Processor act

Re: [gem5-users] Relationship between period size and power

gards, Shervin Message: 1 Date: Fri, 12 Apr 2013 18:52:13 +0100 From: Erik Tomusk > To: gem5 users mailing list > Subject: Re: [gem5-users] Relationship between period size and power Message-ID: <516849cd.1050...@sms.ed.ac.uk > Content-Type: text/plain; ch

Re: [gem5-users] Using a branch predictor

Hi Newton, Do you want to use one of the existing branch predictors, or do you want to write a new branch predictor? Yes, you need to rebuild gem5 after changing .cc files. -Erik On 01/05/13 08:14, Newton Singh wrote: Hi all, I want to use a branch predictor. But i dont know what configura

[gem5-users] Simple cache model and cachePorts limit

Hi All, I've been looking at L1 dcache ports (ports as in the number of read/write requests that a physical cache can service at one time, not ports as the abstraction gem5 uses to connect memory devices). At the moment, the simple cache model will service as many requests as the O3 CPU makes

Re: [gem5-users] Simple cache model and cachePorts limit

Any thoughts? -Erik On 11/05/13 15:14, Ali Saidi wrote: On May 10, 2013, at 11:26 AM, Amin Farmahini <mailto:amin...@gmail.com>> wrote: On Fri, May 10, 2013 at 10:10 AM, Erik Tomusk <mailto:e.tom...@sms.ed.ac.uk>> wrote: *It shouldn't be too difficult to re-

Re: [gem5-users] Simple cache model and cachePorts limit

erned about the number of reads/writes to the L1 than the bandwidth between the L1 and CPU. -Erik On 13/05/13 15:20, Amin Farmahini wrote: Please note that the number of responses from cache to cpu should be limited too. Currently, there is no limit on that. Amin On Mon, May 13, 201

Re: [gem5-users] Questions about Inorder cpu type for ARM

Hi Hongyuan, The short answer is no, the ARM in-order model doesn't work. There's been plenty of discussion on it, so you can search the mailing lists for all the details if you're interested. -Erik On 14/05/13 02:51, Ding, Hongyuan wrote: Hi all, I tried to use the argument "--cpu-type=ino

Re: [gem5-users] Simple cache model and cachePorts limit

I think what I was trying to say is that a cachePorts limit and blocking due to MSHR are independent, and MSHR blocking already exists. I.e. IF (cachePorts available) AND (cache not blocked) AND (cache miss) THEN (still counts as using up a cache port) Alternatively IF (cachePorts available) AND

Re: [gem5-users] Simple cache model and cachePorts limit

I've posted a preliminary patch at http://reviews.gem5.org/r/1872/. Any feedback is much appreciated. -Erik On 15/05/13 12:24, Erik Tomusk wrote: I think what I was trying to say is that a cachePorts limit and blocking due to MSHR are independent, and MSHR blocking already exists. I.e

Re: [gem5-users] error using m5-McPat parser

Hi Rajath, When you say "m5-mcpat parser," I assume you mean Rick Strong's python script . It's been broken for a while and doesn't look like it's actively maintained. I think your best bet is to see what changed in the gem5 config and stats fil

Re: [gem5-users] error using m5-McPat parser

it is working will upload it for the people to use. Regards, Rajath On Mon, May 28, 2012 at 2:43 AM, Erik Tomusk mailto:e.tom...@sms.ed.ac.uk>> wrote: Hi Rajath, When you say "m5-mcpat parser," I assume you mean Rick

Re: [gem5-users] ARM in-order model

Hi Aziz, Someone else might be able to give better advice, but the next thing you should do is probably take a step back. gem5 is complicated enough that blindly hacking in files won't fix anything. To compile the ARM in-order model into gem5, you need this patch: http://reviews.gem5.org/r/1

Re: [gem5-users] question about m5-mcpat-parser-se.py

Take a look at this: http://www.mail-archive.com/gem5-users@gem5.org/msg03878.html -Erik On 05/07/12 21:39, Bojun Ma wrote: Hi,All, Has anyone successfully used m5-mcpat-parser-se.py to convert the simulation refults of gem5 to the input format(.xml) of MCPAT? I has the question abou

Re: [gem5-users] Can I specify the chip floorplan( the location of cores and caches) in gem5?

gem5 doesn't do any sort of floor planning, so it's not that difficult to give gem5 a configuration that isn't practical or even physically possible. You might be interested in "HANDS: Heterogeneous Architectures and Networks-on-Chip Design and Simulation" from ISPLED 2012 (by Zoni, Corbetta,

Re: [gem5-users] Some questions about FS mode multi core simulation?

Hi Bojun, See below On 09/08/12 04:22, Bojun Ma wrote: Hi, All, I have some questions about multi core full system simulation: 1. Is there any way that I can specify the chip area in a CMP configuration? No, gem5 is not aware of area. 2.For ARM FS mode, If I do not use chec

Re: [gem5-users] Problems with McPAT and gem5

Hi Hongyuan, From my personal experience, tool #1 has been broken for quite some time and when I looked at it, it was far too complicated for me to reverse-engineer and fix. I've had much more success with #2, but for various reasons, I can't make my updated version available yet. It probabl

[gem5-users] Redundant branch predictor parameters

Hi All, It seems to me that some of the tournament branch predictor parameters are redundant, at least given how the predictor is currently implemented. Has anyone else run into this? Specifically, the tournament predictor takes nine parameters that can be configured independently: localPre

Re: [gem5-users] Running List of Programs

I have successfully simulated the entire EEMBC 2 Consumer suite on vanilla gem5 in SE mode using ARM. Cheers, Erik On 25/10/12 16:48, Marko Zivkovic wrote: Hello gem5 users, as I stated 3 days ago, I am new in gem5 world. I installed gem5 and my goal was to run ffmpeg application inside of S

Re: [gem5-users] Cortex-A15 Simulation

Hi Robert, That's a very interesting result. Thanks for sharing it. I'm just speculating, but given that the arm_detailed model was added about a year ago, and the A15 is just getting ready to ship now, I suspect the arm_detailed model was tuned to the biggest ARM core available at the time--