[gem5-users] [Ruby memory model] Cache clusivity in MESI

Hi, The gem5 ruby introduction page refers that both MESI 2-level and MESI 3-level as strictly-inclusive caches. https://www.gem5.org/documentation/general_docs/ruby/ Is there any configurability in gem5 to change this behaviour to non-inclusive or it requires to be done by protocol state machine

[gem5-users] Re: [Ruby memory model] Cache clusivity in MESI

Hi gem5 users, Any input or comment on the above query. Regards, Dinesh On Fri, Apr 5, 2024 at 2:19 PM Dinesh Joshi wrote: > Hi, > > The gem5 ruby introduction page refers that both MESI 2-level and MESI > 3-level as strictly-inclusive caches. > https://www.gem5.org/documentation/general_docs/

[gem5-users] [Ruby memory model] FIFO ordering violation

Hi gem5 community, I am exploring the arbitration in between the LLC queues in Ruby Memory Model. Version: 22.0.0.2 CPU target: x86 Memory model: Ruby Configuration: 8 cores num of LLC slices: 8 Therein, I experience FIFO ordering violations. Error message: build/X86/mem/ruby/network/MessageBuffe