[gem5-users] Sharing cache lines at memory level

Hello everyone, I’m an undergraduate student working on a project where I am to evaluate a hardware accelerator my PhD student is working on in a chiplet-based system. We are running garnet2.0, and it would be infeasible to port it to garnet3.0. So far, I’ve had success configuring a chiplet co

[gem5-users] Re: Sharing cache lines at memory level

entation/general_docs/ruby/CHI/ > > In the sidebar you can find descriptions of each of the other protocols as > well. > > Cheers, > Jason > > On Sun, Sep 17, 2023 at 11:32 AM Arteen Abrishami via gem5-users > mailto:gem5-users@gem5.org>> wrote: >>

[gem5-users] MSI Protocol at Memory

Hello everyone I’m an undergraduate student and going to embark on a journey to extend the protocol for MESI_Three_Level at the memory level to MSI or MESI, as opposed to the two-state MI that it is right now. Does anyone have any tips or advice for this journey, perhaps one of you has done som

[gem5-users] mem-ruby: double ACK in MESI_Two_Level

Hello all, I’m working on the MESI_Two_Level protocol and I’ve noticed there is a double ACK process between Memory and L2 For example: L2 receives a MEM_INV L2 deals with it and sends back a clean ACK and goes into the intermediate state Memory receives it Memory sends an ACK to the L2 I was

[gem5-users] Re: Ruby System - HeteroGarnet Debug

You could try RubyQueue. > On Feb 25, 2024, at 10:27 PM, zhangcongwu--- via gem5-users > wrote: > > Hi gem5, > > I am simulating a new cache protocol in ruby system, but my simulation will > occur error when running some parsec benchmark. The error is: > > > I use `--debug-flags=ProtocolTra

[gem5-users] Garnet link latency vs. bandwidth

Hello, Does anyone know if the —link-latency parameter within garnet also affects the bandwidth, or solely the latency? If so, how does this interact with —link-width-bits? Through some experiments, we found that it could potentially be affecting the bandwidth. Best, Arteen __