Re: [gem5-users] DRAMPower results integration with stats.txt

Hi Mohammad, It is indeed. Note that the “--mem-size” does not automatically align with the DRAM configuration, so please take care and make sure the two match up. Andreas On 09/03/2015 14:07, "Mohammad A Khasawneh" wrote: >Hello, > >I was going through the stats.txt file and I saw this line:

Re: [gem5-users] Negative value for system.mem_ctrls_1.actEnergy

Hi Majid, First I would suggest to check the IDD values. Perhaps there is a typo somewhere, or even an inconsistency in the actual data sheet. Second it would be good to know if you're doing any form of check pointing. If so there could be something not getting reset properly. Andreas - O

Re: [gem5-users] Forwarding data from strd to ldrd

I must confess I am not too familiar with how the various CPUs accomplish this. Hopefully someone else is able to help. Andreas From: Vanchinathan Venkataramani mailto:dcsv...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Wednesday, 11 March 2015 09:22 To: gem

Re: [gem5-users] How long does it take to run Frozen Bubble c AsimBench

Hi Anmol, The detailed o3 CPU is roughly 10x slower than atomic, so ~5 days seems likely. Andreas From: Anmol Mohanty mailto:anmol.eece.iit...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Wednesday, 11 March 2015 23:12 To: "gem5-users@gem5.org

Re: [gem5-users] Negative value for system.mem_ctrls_1.actEnergy

Hi guys, If we want to stick to a x8 4Gb part, then perhaps K4A4G085WD-BCRC would make sense? Andreas From: Majid Jalili mailto:majid...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Thursday, 12 March 2015 07:17 To: omar naji mailto:naji_o...@hotmail.com>> C

Re: [gem5-users] Integrating image sensor

Hi Navin, That sounds like a great plan. Hopefully this will help: http://reviews.gem5.org/r/2700/ Andreas From: Navin Senguttuvan mailto:senguttu...@wisc.edu>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Tuesday, 17 March 2015 06:51 To: Gem5 Users Mailing List mailto:

Re: [gem5-users] ARM : Hang while booting arm_detailed quadcore CPU

Hi Lokesh, I suspect the kernel you are using is not compatible with the disk image in question. We should have instructions for how to run KitKat online shortly, along with pointers to a recent kernel (with DVFS support etc). Andreas From: Lokesh Jindal mailto:lokeshjinda...@cs.wisc.edu>> R

Re: [gem5-users] Integrating image sensor

: Gem5 Users Mailing List mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Integrating image sensor ​​Andreas, That should definitely help. Thanks a lot ! Navin From: gem5-users mailto:gem5-users-boun...@gem5.org>> on be

Re: [gem5-users] In Order and O3 CPU

Hi Naveed, I think there is some confusion here between hardware threads and software threads. The MinorCPU, at the moment, does not support hardware multi-threading. It has no issues running multi-threaded software. I hope that addresses your concern. Andreas On 20/03/2015 16:43, "Naveed Ul M

Re: [gem5-users] Counting cache misses runtime

Hi Nimish, When you say “count at runtime”, do you mean 1) in the software on the guest, or 2) just in a simulated hardware module? For #1 I would suggest to add them as PMU counters, and #2 you can use the probe infrastructure and a custom probe listener. Andreas From: Nimish Girdhar mailto:

Re: [gem5-users] Counting cache misses runtime

you explain it a >>bit >more... >> Thanks, >> On Mar 24, 2015 3:00 AM, "Andreas Hansson" >>arm.com> >wrote: >> >> >> >> >> Hi Nimish, >> >> When you say “count at runtime”, do you mean 1) in the software on the &

Re: [gem5-users] Miss rate douby

Hi Matheus, Are you dumping stats (or exiting) after some specific number of instructions (I.e. are you doing the same amount of work)? Also, if you are using the default o3 configuration it is very aggressive, so perhaps the latency can be hidden? Andreas From: Matheus Alcântara Souza mailto

Re: [gem5-users] Miss rate douby

mailto:ticks...@gmail.com>> Date: Thursday, 26 March 2015 14:24 To: gem5 users mailing list mailto:gem5-users@gem5.org>>, Andreas Hansson mailto:andreas.hans...@arm.com>> Subject: Re: [gem5-users] Miss rate douby Maybe the problem is the use of Atomic CPU. I'll try to use Timing on

Re: [gem5-users] SystemC Co-Simulation

Hi Matthias, It should be fixed now. A “public” was missing in the inheritance for the InstPBTrace. Andreas On 26/03/2015 12:41, "Matthias Jung" wrote: >Hi, > >I just want to try the SystemC coupling example provided in: >gem5/util/systemc >I followed the instructions of the README file. > >Du

Re: [gem5-users] Tracking DRAM requests from a process

Hi Prathap, Could you be a bit more specific about what you mean by “tracking requests”. Each request that originates in the CPU has an ASID and ThreadID associated with it, as well as a MasterID. You should be able to access these at the DRAM controller if that’s what you’re after. Note that y

[gem5-users] gem5 User Workshop 2015 at ISCA-42

ns on progressing identified pain points [1.5 hours] * Wrap-up and next steps [45 minutes] More information will be available at: http://www.gem5.org/User_workshop_2015 We look forward to your contributions and hope to see you there. Workshop organisers: Ali Saidi, ARM Andreas Hansson, ARM Anthony Guti

[gem5-users] gem5 User Workshop 2015 at ISCA-42

oints [1.5 hours] * Wrap-up and next steps [45 minutes] More information will be available at: http://www.gem5.org/User_workshop_2015 We look forward to your contributions and hope to see you there. Workshop organisers: Ali Saidi, ARM Andreas Hansson, ARM Anthony Gutierrez, AMD Nilay Vaish, Un

Re: [gem5-users] memory access time

Hi Marziye, If you are using the DRAMCtrl (in any configuration), then you have avgQLat, avgBusLat and avgMemAccLat that breaks down the memory access time. Andreas From: marziye esmslampanah mailto:mesmslampa...@yahoo.com>> Reply-To: marziye esmslampanah mailto:mesmslampa...@yahoo.com>>, gem

Re: [gem5-users] memory access time

and avgMemAccLat)? And another question is how did you calculate for example the avgQLat? what is the dimension of this parameter? and did you calculate the miss cache time for avgQLat in your experiments? Thanks in advance. On Wednesday, 8 April 2015, 11:08, Andreas Hansson mailto:andreas

Re: [gem5-users] bytesWritten < (8 * number of 64-bit stores to unique addresses)

Hi Patrick, When it comes to the stores you are looking at a rather small number of operations, and my guess is that they are still in the DRAM write queues. These queues are not drained at the moment once the writes fall below the “low water mark”. Andreas From: Patrick mailto:plafr...@gmail

Re: [gem5-users] DVFS with self defined policies on gem5

Hi all, The nice and clean option would be to use add an architecturally visible performance counter read from the DVFS governor (in software). The hackish option is to change the clock speed behind the back of the OS, by having the DVFSHandler object change the clocks based on e.g. a probe poi

Re: [gem5-users] ARM - Cache Coherence Protocol

Hi Davesh, With ARM you should use the classic memory system (in some configuration), and thus a MOESI protocol. There is no need to use Ruby. The cache and crossbar models in the classic memory system provide a very flexible set of components that you can use to build a wide range of on-chip

Re: [gem5-users] ARM - Cache Coherence Protocol

com/t?sender=ac2hpbmdhcmlkYXZlc2hAZ21haWwuY29t&type=zerocontent&guid=88aed3a1-1370-47f1-b943-aa2ce935efc0]ᐧ On Wed, Apr 15, 2015 at 4:31 PM, Andreas Hansson mailto:andreas.hans...@arm.com>> wrote: Hi Davesh, With ARM you should use the classic memory system (in some configuration), and

Re: [gem5-users] ARM - Cache Coherence Protocol

9499-4c2c-830d-80ef7a89077c]ᐧ On Wed, Apr 15, 2015 at 5:03 PM, Andreas Hansson mailto:andreas.hans...@arm.com>> wrote: Q1 Since you are not using Ruby the PROTOCOL is irrelevant Q2 As with all gem5 objects there is a Python class (BaseCache.py) instance created. Check out CacheConfig

Re: [gem5-users] [gem5-dev] ARM DVFS : Core dead time and Voltage change time

Hi Lokesh, gem5 does indeed currently only capture the delay in the transition, and still “clocks” the components that are affected. A more detailed model of the PMIC and voltage regulators, battery etc can definitely be added, the transitions refined etc. The question is how much it matters, and

Re: [gem5-users] ARM - Cache Coherence Protocol

nges other places too i.e. should I make these request uncacheable everywhere isUncacheable is being checked? Thanks for your time. -- Have a great day! Thanks and Warm Regards Davesh Shingari Master's in Computer Engineering [EE] Arizona State University dshin...@asu.edu<

Re: [gem5-users] Regarding outstanding request queue at coherent_bus.cc

Hi Biswabandan, I do not understand the idea of having a single packet for X and X+1. Surely you break the coherency protocol if you do this and suddenly end up with a 128 byte request. To me it sounds like you are creating a next-line prefetcher, but in a very painful way. Am I missing someth

Re: [gem5-users] Configurating memory system

Hi Marcos, This should be fine. Simply associate the cache with a memory range [0:cache_range] and each scratch pad with [scratch_range1:scratch_range2] etc for each core. The system memory will then also be [0:cache_range]. Creating the hardware should be easy. The real challenge will be in havin

Re: [gem5-users] ARM - Cache Coherence Protocol

I know the implementation is brittle and is temporary. I will be modifying it to make it stable and configurable. On Thu, Apr 16, 2015 at 6:21 PM, Andreas Hansson mailto:andreas.hans...@arm.com>> wrote: Hi Davesh, Conceptually it looks ok (but rather brittle using a number like that). You

Re: [gem5-users] Regarding outstanding request queue at coherent_bus.cc

sers mailing list mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Regarding outstanding request queue at coherent_bus.cc Hi Andreas, I am transferring 64 bytes only. The packet contains compressed data. On 20 Apr 2015 18:18, "Andreas Hansson" mailto:andreas.hans...@arm.com

Re: [gem5-users] ARM - Cache Coherence Protocol

patches. Thanks again for your help. [https://mailfoogae.appspot.com/t?sender=ac2hpbmdhcmlkYXZlc2hAZ21haWwuY29t&type=zerocontent&guid=a50c2c8c-7776-46f6-ac94-62cb9638b94a]ᐧ On Mon, Apr 20, 2015 at 5:52 AM, Andreas Hansson mailto:andreas.hans...@arm.com>> wrote: Hi Davesh, There is a wh

Re: [gem5-users] PMU in GEM5

Hi Kumail, Yes, it works just fine. All you have to do is create the PMU, and add the events. Something along the lines of: for isa in cpu.isa: isa.pmu = ArmPMU() isa.pmu.addArchEvents( cpu=cpu, dtb=cpu.dtb, itb=cpu

Re: [gem5-users] About GemFI

I’d encourage the authors/creators to contribute their patches to mainline gem5. That way it is easier to use, maintain and further develop. Andreas From: 郑潇逸 mailto:xyinthemom...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Wednesday, 29 April 2015 02:51 To:

Re: [gem5-users] problem with gem5.debug

Hi Kassan, It would be good if you could elaborate on what “does not work” actually means and how it manifests itself. Andreas From: kassan unda mailto:kassanu...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Wednesday, 29 April 2015 23:38 To: gem5 users mail

Re: [gem5-users] problem with gem5.debug

ithout the location dependencies. Appreciate your response. On Apr 30, 2015 2:35 AM, "Andreas Hansson" mailto:andreas.hans...@arm.com>> wrote: Hi Kassan, It would be good if you could elaborate on what “does not work” actually means and how it manifests itself. Andreas From: kassan

Re: [gem5-users] Cache Flushing in FS-ARM

Hi Erfan, The cache management instructions are currently not implemented. It would be a great addition though. The only related instruction that is currently supported is dzcva. If you’re interested in filling in the blanks I’m sure there are plenty people willing to help out. All devices in

Re: [gem5-users] Query regarding blocking cache slave port

Hi Prathap, The most sensible place to implement the arbitration is indeed in the crossbar which is conceptually part of the L2 cache. By default the crossbar uses First-Come First-Served, but you can change with not too much coding. The tricky bit in this case is to base the selection on MSHRs

Re: [gem5-users] Query regarding blocking cache slave port

e port Hi Andreas, Thanks for your reply. I am trying to figure out how to implement this based on your inputs. Can you also please point out the data structures which maintains the queue in cross bar.? Thanks, Prathap On Mon, May 4, 2015 at 4:04 PM, Andreas Hansson mailto:andreas.hans...@a

Re: [gem5-users] Android ICS and gingerbread error while boot

Hi Junaid, Is it hanging, or just taking its time? Andreas From: Junaid Shuja mailto:junaidsh...@siswa.um.edu.my>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Thursday, 7 May 2015 05:45 To: "gem5-users@gem5.org" mailto:gem5-users@gem5.org>>

Re: [gem5-users] gem5-users Gem5 boot time

Hi all, This sounds very odd. I ran the following this morning: build/ARM/gem5.opt configs/example/fs.py This gives me a login prompt within roughly 80 seconds on a not-so-impressive workstation. Note that this is running on the atomic CPU, and using all the default options. Andreas From: Ju

Re: [gem5-users] Time sharing between cores

Hi Kumail, Could you elaborate on what it is you want to simulate? gem5 supports multi-processor systems, and for ARM it even support heterogeneous processors (e.g. a number of in-order cores combined with a number of out-of-orded cores). You just have to make sure you have a suitable kernel a

Re: [gem5-users] ARM build options

Hi Junaid, What errors are you encountering? Andreas From: Junaid Shuja mailto:junaidsh...@siswa.um.edu.my>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Monday, 11 May 2015 10:36 To: "gem5-users@gem5.org" mailto:gem5-users@gem5.org>> Subjec

[gem5-users] Upcoming gem5 workshop at ISCA

Hi all, For those attending the user workshop at ISCA, please note that the early registration deadline (18th of May) is approaching quickly. If you have not yet decided, the program is found here: http://www.gem5.org/User_workshop_2015 We hope to see you in Portland and look forward to an enga

Re: [gem5-users] Where is file pipeline_stage.cc in source tree

Hi Kaiyuan, The old InOrderCPU model is retired, and consequently removed from the source tree. Please use the MinorCPU instead. It will be renamed to InOrderCPU shortly. Andreas On 16/05/2015 11:37, "Liang Kaiyuan" wrote: >Hello, all > >I am newbie to gem5. I downloaded source code and revie

Re: [gem5-users] X86 In Order CPU Model

It boots linux and runs the regressions. In other words, it should be just fine. Andreas From: Ayaz Akram mailto:aaq...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Thursday, 21 May 2015 15:34 To: "gem5-users@gem5.org" mailto:gem5-

Re: [gem5-users] about DVFS Futher Experiments in Per-core DVFS

Hi Bing Liang, The socket_id is a parameter on the BaseCPU object, and you set it like any other parameter, e.g. system.cpu[1].socket_id = 1 Andreas From: 冰兲轌地 <553024...@qq.com> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Tuesday, 26 May 2015

Re: [gem5-users] protobuf inline header not defined

Hi Kassan, You should not have to change anything in gem5, assuming you have installed protobuf properly. Andreas From: kassan unda mailto:kassanu...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Tuesday, 2 June 2015 14:14 To: gem5 users mailing list mailto:g

Re: [gem5-users] protobuf inline header not defined

i Rolla) WebPage: http://web.mst.edu/~kutx9 "Do not go where the path may lead, go instead where there is no path and leave a trail." Ralph Waldo Emerson On Tue, Jun 2, 2015 at 2:17 PM, Andreas Hansson mailto:andreas.hans...@arm.com>> wrote: Hi Kassan, You should not have to chan

Re: [gem5-users] Error: Undefined reference to `vtable for CommMonitor'

Hi Azadeh, It sounds like you’ve got something wrong with the comm_monitor.cc file. Make sure you have the appropriate version (hg revert src/mem/comm_monitor.cc). Also, you do not need to change the comm monitor to trace packets. It’s already part of its functionality. Andreas From: Azadeh S

Re: [gem5-users] Copy memory out of simulation

Hi Guru, If you are talking about guest physical address, then it should be very easy, as it is a linear mapping to the host. The KVM CPU uses this fact quite extensively. Depending on where you want to do this, the easiest may be to create a PortProxy and simply read it out. Andreas From: Gu

Re: [gem5-users] Copy memory out of simulation

ny of the reads/writes. Could you point me to an example of PortProxy implementation? Like I mentioned earlier, I tried using the fs_translating_port_proxy functions which didn't work out. Regards Guru On Wed, Jun 10, 2015 at 3:37 AM, Andreas Hansson mailto:andreas.hans...@arm.com&g

Re: [gem5-users] How to run SMT in ARM SE mode?

Hi, I suspect the SMT support is a bit shaky. There are a number of patches and discussions on the review board that might help. Andreas On 12/06/2015 09:13, "n26001482" wrote: >hi, all > >I've tried to run SMT in ARM SE mode. But it didn't work. > >This is the command I typed > >gem5.opt ~/ge

Re: [gem5-users] To get O3CPU ptr in memory system.

Hi MinKyu Lee, If you want to do this “properly”, I would suggest to use ProbePoints. There is a good infrastructure for getting this type of information, and the interface is very generic. You could create probe points in the CPU objects, and then register your custom probe to get the informat

Re: [gem5-users] L2 cache partitioning

Hi Prathap, We have some patches to restrict way allocation in the cache itself (not per core though). You can probably use that as a starting point. I’m afraid beyond that you will need to add the appropriate functionality to look at e.g. masterId and decide on a way. I’ll try and get those pa

Re: [gem5-users] Error in compiling gem5.debug

Hi Kaiyuan, I suspect you ran into this: http://stackoverflow.com/questions/3025997/defining-static-const-integer-members-in-class-definition In opt and fast the values get inlined and we have no problem. In debug, they point to nothing since we do not have an out-of-class declaration. In fact

Re: [gem5-users] SOC design questions

Hi Vivian, I would suggest your best option is to stick with the classic (non-Ruby) memory system, and use the CommMonitor for packet tracing. Andreas On 16/06/2015 20:51, "chelin" wrote: >HI there > >I'm trying to simulate a post silicon SOC validation by creating my own >platform and monitor

Re: [gem5-users] Dynamic frequency change

Hi Simone, The method does not exist in Python. Remember that essential all objects in gem5 have both a Python object (used for setting parameters mostly), and a C++ object (actually involved in the simulation). In general you should either use full-system and leave the DVFS to the OS (I would

Re: [gem5-users] ARM KVM support

Hi Junaid, That was a long time ago… The aarch64 KVM cpu model should be working just fine (in full-system mode). Andreas From: Junaid Shuja mailto:junaidsh...@siswa.um.edu.my>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Thursday, 18 June 2015 00:33 To: "gem5-users@g

Re: [gem5-users] Physical address too long!!!!

Hi Kassan, Perhaps I have misunderstood your question… Why on earth would the address be in the range [0 : 64 kByte] ? Just because the cache is small does not mean it holds addresses in any specific range. Andreas From: kassan unda mailto:kassanu...@gmail.com>> Reply-To: gem5 users mailing li

Re: [gem5-users] How to model a die-stacked DRAM?

Hi Prathap, The DRAM controller in gem5 is flexible enough to support die-stacked memories, all you need is to specify suitable timing and architecture parameters. You already find a WideIO model, as well as an HMC vault model. You should be able to add WideIO2 and HBM without much effort (just

Re: [gem5-users] Print packet information

Hi Cao, The CommMonitor already has tracing support (using an efficient protobuf format). The trace format is defined by src/proto/packet.proto and you can see how it is populated in src/mem/comm_monitor.cc. If you want to add any fields it is very straight forward. Just remember that your traces

Re: [gem5-users] How to configure three level caches with different cache line size?

Hi Will, The classic memory system requires all coherent caches to have the same line size. Thus, all your L1s, L2s etc need to have the same cacheline size, and there isa parameter on the system level to set it. If you want your last-level cache to have a larger cache you can do so, but it re

Re: [gem5-users] gem5 Governance document: a request for comments

Hi Jason, I will definitely have a look next week. If you’re fine with holding off for a few more days that’d be great. Thanks, Andreas From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of Jason Power mailto:power...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-us

Re: [gem5-users] Uncachable Load

Hi Shamik, Are you using the most up-to-date gem5? There were recently quite some changes around how uncacheable accesses (vs strictly-ordered device accesses) are handled. Andreas From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of Shamik Saha mailto:shmk_s...@yahoo.co.in>> R

Re: [gem5-users] Uncachable Load

Hi Shamik,That's the one.Andreas From: Shamik Saha Reply-To: Shamik Saha , gem5 users mailing list Date: 6/27/15, 11:39:09 AM GMT+2 To: gem5-users@gem5.org Subject: Re: [gem5-

Re: [gem5-users] Wakeup after restoring checkpoint

Hi all, Have a look at http://www.gem5.org/SimObject_Initialization and src/sim/sim_object.hh. In general, I would recommend to not schedule events in init(), and rather do so in initState, loadState or startup. Andreas From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of Erfan

Re: [gem5-users] Help to understand memory trace

Hi Prathap. Have a look at src/proto/packet.proto. The ASCII output is not really intended to be used for anything besides “checking”. The fields in the trace correspond to the enums in src/mem/packet.hh and src/mem/request.hh Andreas From: gem5-users mailto:gem5-users-boun...@gem5.org>> on

Re: [gem5-users] Classic memory mode cache communication

Hi Cao, I think you have misinterpreted something in the traces. The only packets going between the I and D cache of a CPU are snoops. Andreas On 05/07/2015 04:52, "gem5-users on behalf of cao2" wrote: >Hi there > >I have a platform with two cpu with its own icache and dcache and one >classic

Re: [gem5-users] SE mode protocol

Hi Cao, Ruby does not work with ARM (due to assumptions about the memory layout). Thus, stay with the classic memory system. Andreas On 05/07/2015 04:55, "gem5-users on behalf of cao2" wrote: >Hi there > >I'm trying to run the se mode with moesi_cmp_directory protocol, I did it >by run "scons

Re: [gem5-users] DRAM Memory dual port

Hi Marcos, I am not sure what you are asking for. If you want a multi-ported controller (as in more than one system interface) for a single DRAM channel, then you can either rely on the existing system ‘bus’ (which is really a crossbar), or instantiate an additional crossbar in front of the memor

Re: [gem5-users] SystemXBar latency

Hi Yuting, The short answer: for requests, no. The long answer: You may have seen that I just pushed a patch that adds latency in the crossbar on the response path. In essence we just use a queued port to hold on to the packets until they are supposed to be sent. The reason it is challenging to

Re: [gem5-users] Multiple sets of simulation statistics getting populated in stats.txt

Hi Rahul, When you run full-system, the whole point is that the OS is present. This invariably means that there will be background tasks happening besides what ever benchmark you are running. It’s simply something you have to take into account if you want your experiment to be realistic. Andre

Re: [gem5-users] [gem5 users] a query regarding tag in Mcpat xml for ARM FS simulation

Hi Rahul, I do not believe McPAT supports DVFS properly, so in any case your mileage may vary. My guess would be that target_core_clockrate is what the cores where designed to achieve as their max clock rate. Andreas From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of rahul s

Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus

Hi Prathap, The expression ensures that we do not “go back in time” when deciding to precharge the bank. If we have not already precharged, we need to take the hit and do it now. For the access pattern you describe, with an closed-adaptive or open-adaptive page policy we will issue the last col

Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus

its left in the queue? I agree that with open-adaptive policy, the Bank1 will be auto precharged. According to the code snippet below, it still has to issue an activate now. Shouldn't this have done back in time(Bank level parallelism)? Thanks, Prathap On Fri, Jul 10, 2015 at 2:16

Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus

p sooner than we have to. nextReqTime = busBusyUntil - (tRP + tRCD + tCL); Thanks, Prathap On Fri, Jul 10, 2015 at 11:51 AM, Andreas Hansson mailto:andreas.hans...@arm.com>> wrote: Hi Prathap, If we have no row hits left in the queue, the open-adaptive (and close-adaptive) policy will auto precharge

Re: [gem5-users] Question on retry requests due to write queue full.

Hi Prathap, Your write are probably arriving faster than the controller can actually send them to the DRAM. What is it you’re running? Andreas From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of Prathap Kolakkampadath mailto:kvprat...@gmail.com>> Reply-To: gem5 users mailing li

Re: [gem5-users] MSHR Queue Full Handling

Hi Davesh, 1. The promoteDeferredTargets is a “trick” used in the classic memory system where MSHR targets gets put “on hold” if we already have a target outstanding that will e.g. give us a block in modified or owned state. Once the first chunk of targets are resolved, and all caches agree

Re: [gem5-users] MSHR Queue Full Handling

Hi all, The best way to customise your L1 instances is in the config script itself. If you use fs.py, I’d suggest to do it there. Andreas From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of Prathap Kolakkampadath mailto:kvprat...@gmail.com>> Reply-To: gem5 users mailing list m

Re: [gem5-users] DRAMCtrl: Question on read/write draining while not using the write threshold.

Hi Prathap, It sounds like something is going wrong in your write-switching algorithm. Have you verified that a read is actually showing up when you think it is? If needed, is there any chance you could post the patch on RB, or include the changes in a mail? Andreas From: gem5-users mailto:g

Re: [gem5-users] Could cache connected without bus?

Hi Will, In general you should be fine to connect two caches back to back. The question is, why would you? Why not make one of the caches larger? Andreas From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of Will mailto:alpha0...@yeah.net>> Reply-To: gem5 users mailing list mail

Re: [gem5-users] Stream benchmark in SE mode, bandwidth does not degrade when run in parallel

Hi Timo, As a general rule, never use any performance number from atomic mode. Atomic mode is for fast forwarding and warming (and for anything non-temporal). The only notion of time is ‘enough to not confuse the OS’. I would recommend to re-run your experiment with a realistic timing core model

Re: [gem5-users] Stream benchmark in SE mode, bandwidth does not degrade when run in parallel

t 21:33 +0100, Andreas Hansson wrote: > >Hi Andreas, > >> As a general rule, never use any performance number from atomic mode. >> Atomic mode is for fast forwarding and warming (and for anything >> non-temporal). The only notion of time is ‘enough to not confuse the >&

Re: [gem5-users] Why cache misses are decreasing when core frequency increase?

Hi Nimish, How do you determine cache misses (what stat are you looking at)? Are you running the same workload in the two scenarios (i.e. are the actual instructions executed the same)? Is it full system (and if so, are you changing the core frequency without the OS knowing about it)? Can you

Re: [gem5-users] Why cache misses are decreasing when core frequency increase?

g as I am able to do that, I should be okay. That's why I need some help with the reasoning as to why I am seeing the above stats? Any thoughts? Thanks, On Thu, Jul 16, 2015 at 3:06 PM, Andreas Hansson mailto:andreas.hans...@arm.com>> wrote: Hi Nimish, How do you determine cache mi

Re: [gem5-users] Handling write backs

Hi Prathap, When you write with a granularity smaller than a cache line (to your L1 D cache), the cache will read the line in exclusive state, and then write the specified part. If you write a whole line, then there is no need to first read. The latter behaviour is supported for whole-line writ

Re: [gem5-users] [DRAM] FRFCFS: Reordering Request Queue & Bank Parallelism

Hi Davesh, 1. Yes. 2. If we find a row-hit that can be performed seamlessly we stop the iteration. In all other cases, we iterate over the entire queue. The selection is guided by minBankPrep. 3. Bank parallelism is achieved by looking at the requests to all banks. Try running build/NULL

Re: [gem5-users] How queued port is modelled in real platforms?

Hi Prathap, The queued port is indeed infinite, and is a convenience construct. It should only be used in places where there is already an inherent limit to the number of outstanding requests. There is an assert in the queued port to ensure things do not grow uncontrollably. Andreas From: gem

Re: [gem5-users] How queued port is modelled in real platforms?

rface protocol specifies this limit in real platforms? Thanks, Prathap On Mon, Jul 27, 2015 at 4:54 AM, Andreas Hansson mailto:andreas.hans...@arm.com>> wrote: Hi Prathap, The queued port is indeed infinite, and is a convenience construct. It should only be used in places where there is al

Re: [gem5-users] ARM KVM support

Hi Junaid, I think you’ve manage to confuse the instruction set and the CPU model. To run with KVM, you need to specify the ArmKvmCPU as the CPU type. Needless to say, this means you need to build and run on an ARM host. Andreas From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf

Re: [gem5-users] fault injection problem.

Hi all, I would like to grab this opportunity to encourage anyone extending gem5 in any shape or form to contribute their changes back to the main repository. That way we can ensure broader compatibility, continued support and regression testing, and a much larger audience. If you did all the hard

Re: [gem5-users] Gem5 ATAG error

Hi Abdul, This touches on a pretty fundamental issue. The external port works fine for connecting devices, but when connecting a memory, there are a number of assumptions in gem5 that will give us problems. You have run into the first one which is that gem5 needs to be aware of the memory to re

Re: [gem5-users] Reducing time taken by dual simulations

Hi Guru, To speed things up, here are some options: 1. Use atomic to get the point of interest, then take a checkpoint. Is this what you are doing? 2. For the above, run with --fast-mem since you’re not warming any caches anyways. 3. If possible, use the KvmArmCPU instead of (1). This should gi

Re: [gem5-users] Reducing time taken by dual simulations

t. >Is using KvmArmCPU as simple as just saying --cpu-type=...? >I ask this because --list-cpu-types for my current version only displays >timing => TimingSimpleCPU >detailed => DerivO3CPU >atomic => AtomicSimpleCPU >minor => MinorCPU > > >Rega

Re: [gem5-users] Gem5 ATAG error

the ranges of external memory. That's resolved the issue. I don't know if it is the right solution. Thanks 2015-08-03 14:56 GMT+02:00 Andreas Hansson mailto:andreas.hans...@arm.com>>: Hi Abdul, This touches on a pretty fundamental issue. The external port works fine for connecti

Re: [gem5-users] Reducing time taken by dual simulations

2 >> >>I don't think I have KvmArmCPU available. I will try the same with the >>latest. >>Is using KvmArmCPU as simple as just saying --cpu-type=...? >>I ask this because --list-cpu-types for my current version only displays >>timing => TimingSimpleCPU >&g

Re: [gem5-users] CPU and L1-d Cache Trace

Hi Hamed, If you change the py files in src you need to recompile gem5 before running. You do not need the debug flag to get the trace. Hope that helps. Andreas From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of Hamed Ghadimi mailto:hamed_ghad...@yahoo.com>> Reply-To: Hamed G

Re: [gem5-users] Sources of In-determinism in Full System Simulators

Hi Prathap, That sounds very odd and should not happen unless the workload itself is somehow random. What is it you are running? Are you sure you’re running exactly the same thing? If it does indeed vary then it would be good if you can track down why by running two simulations in lock-step an

Re: [gem5-users] MPSoC

Hi Leila (I hope I got that right), 1. Simulating on a 64-bit host machine is better, simply for speed reasons. gem5 should work on a 32-bit host, but it will hamper performance. 2. You can simulate pretty much _any_ system topology, big cores, little cores etc. What you cannot do at the mom

Re: [gem5-users] gem5-users Digest, Vol 109, Issue 16

person managing the list at gem5-users-ow...@gem5.org<mailto:gem5-users-ow...@gem5.org> When replying, please edit your Subject line so it is more specific than "Re: Contents of gem5-users digest..." Today's Topics: 1. MPSoC (leila zamani) 2. Re: MPSoC (Andreas

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