Hi all,
I am implementing my own architecture starting on the O3 model in gem5, and
I need a Write Combine Buffer for it to work properly.
Since I think is a rather common feature, I was wondering if any
implementation of such structure is available (maybe with a different name?)
or if I need to im
lt;http://grok.gem5.org/source/s?defs=DPRINTF&project=m5>(Fetch
<http://grok.gem5.org/source/s?defs=Fetch&project=m5>, "[tid:%i]:
fault (%s) detected @ PC %s.\n",691
<http://grok.gem5.org/xref/m5/src/cpu/o3/fetch_impl.hh#691>
tid <http://grok.gem5.org/source/s?defs=tid&project=m5>, fault
<http://grok.gem5.org/source/s?defs=fault&project=m5>->name
<http://grok.gem5.org/xref/m5/src/cpu/o3/fetch_impl.hh#name>(), pc
<http://grok.gem5.org/xref/m5/src/cpu/o3/fetch_impl.hh#pc>[tid
<http://grok.gem5.org/source/s?defs=tid&project=m5>]);
>From this snapshot looks like the fault will be carried on to the commit
stage by a noop. However, I cannot understand where such instruction is sent
to, as the object "instruction" is not stored anywhere else.
Can anybody help me understand how such traps are supposed to work?
Thank you very much,
-Andrea Pellegrini
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te:
> I took a quick look at this code and didnt see anything obvious (although
> the translation additions are more recent than I've been paying close
> attention).
>
> Gabe?
>
> On Wed, Oct 26, 2011 at 2:43 PM, Andrea Pellegrini <
> andrea.pellegr...@gmail.co
Hi all,
I just downloaded the latest version of gem5, as I wanted to start w/ a
fresh version of the simulator.
I am testing some basic functionalities that I need for my simulations - my
target is X86_SE. One of such is the possibility of "fast-forward" through
a bunch of instructions.
I remember
I can boot the O3 model multicore, but the system is highly unstable and
often it gets stuck or crashes. I attached a couple of logs from my
experiments.
The single core detailed model seems to work well.
-Andrea
x86_64-vmlinux-2.6.28.4.smp
Hi all,
I am doing some experiments w/ SMT and X86 in SE mode. I found something
funny happening w/ the register file, that I wanted to clarify.
Arch register 16 seems to be assigned always to the zeroRegister in the
rename phase. In the renaming logic, reg 16 is always renamed to the same
physic
ous how that worked
>> with alpha.
>>
>> Thanks,
>> Ali
>>
>> Sent from my ARM powered mobile device
>>
>> On Jun 22, 2012, at 6:22 PM, Andrea Pellegrini <
>> andrea.pellegr...@gmail.com> wrote:
>>
>> Hi all,
>>
>&g
happening when there is a mispredict and a
> return to architected state. If you don't run into problems with this fix
> over the next few days could you post a patch to the review board (
> reviews.gem5.org)?
>
>
>
> Thanks,
>
> Ali
>
>
>
> On 27.06.2012 1
I am incurring in the same error... was it fixed?
I wish I could fix this problem w/o updating the entire repository -
unfortunately I made heavy changes to the whole O3 core and I don't think
it will be easy to move to a newer gem5 version
-Andrea
On Sun, Jan 22, 2012 at 1:25 PM, Mahmood Na
Hi Ali,
I got SMT to work on x86. How can I submit a patch to be reviewed?
Thanks,
-Andrea
On Wed, Jun 27, 2012 at 11:32 AM, Andrea Pellegrini <
andrea.pellegr...@gmail.com> wrote:
> Ali, that it is correct.
>
> I will keep track of these changes to post a review in a few days. T
lto:gem5-users-boun...@gem5.org] *On
> Behalf Of *Andrea Pellegrini
> *Sent:* 28 June 2012 22:55
> *To:* sa...@umich.edu; gem5 users mailing list
> *Subject:* Re: [gem5-users] ZeroReg problem
>
> ** **
>
> Hi Ali,
>
> I got SMT to work on x86. How can I submit
which I
> used in January. A possible solution is to revert your changes and
> find the break point. Then you can describe more about your problem.
>
> On 6/28/12, Andrea Pellegrini wrote:
> > I am incurring in the same error... was it fixed?
> >
> > I wish I could fi
Hi all,
I am facing a bizarre issue w/ X86, SE, O3.
On my laptop the simulator works fine, but when I run gem5 on our
simulation pool I almost always get "fatal: Out of memory, please increase
size of physical memory".
Of course I recompile everything from scratch when I run gem5 on our
servers.
before
> you send to the cluster.
>
> Lastly, Ali is right in that you should check to see that your program
> isnt simply leaking memory too (valgrind!).
>
> On Tue, Jul 24, 2012 at 11:55 AM, Andrea Pellegrini
> wrote:
> > Hi all,
> > I am facing a bizarre issue
Found the problem.
It was an issu with pagePtr not being initialized in system.cc -
http://www.mail-archive.com/gem5-dev@gem5.org/msg02833.html
Thanks again for your help guys!
-Andrea
On Tue, Jul 24, 2012 at 3:55 PM, Andrea Pellegrini <
andrea.pellegr...@gmail.com> wrote:
> Ali, Kore
Hi Weal,
I was able to run some mibench, SPEC2000 and SPEC2006 benchmarks. In order
to do that you will need to compile them statically and apply to gem5 some
patches that modify the syscalls (I believe they are from Vince Weaver -
for instance http://reviews.gem5.org/r/588/).
Good luck!
-Andrea
ec.org/cpu2000/
>> but the issue that is not clear to me is how to apply to gem5 some
>> patches that modify the syscalls ?
>>
>> Thank you in advance for your time.
>> Best Regards
>> Wael AMR
>>
>>
>> On Wed, Jul 25, 2012 at 3:14 PM, And
Hi all,
I am wondering if there is any quick way to increase the number of ports of
a O3 CPU to the ICache and DCache (or mimic a similar behavior).
Did anyone look at it yet?
Thanks,
-Andrea
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Hi Arthur:
interesting, I don't recall seeing this behavior in my experiments (it
seems to happen very soon). Can you share a little bit more about your
setup, so I could try to reproduce this issue? Are you running an
unmodified gem5 model?
Thanks,
-Andrea
On Thu, Sep 27, 2012 at 12:11 PM, Arth
Hi Mike,
I made some modifications myself to support SMT on O3 on X86.
After applying this patch (http://reviews.gem5.org/r/1281/#review2999) I
had no issued running SMT in SE mode -- at least in my tests.
-Andrea
On Thu, Sep 27, 2012 at 10:02 AM, Yuval H. Nacson <
yhnac...@tx.technion.ac.il> wrot
input but this is not relevant to the issue I
> am seeing here.
> I hope it helps and let me know if you need any more information.
>
> Thank you,
> Arthur Perais.
>
>
> Le 28/09/2012 21:09, Andrea Pellegrini a écrit :
>
> Hi Arthur:
>
> interesting, I don't
s you do at least. You can just send the
benchmark at: andrea pellegrini @ gmail com
Thanks!
-Andrea
On Fri, Sep 28, 2012 at 5:10 PM, Andrea Pellegrini <
andrea.pellegr...@gmail.com> wrote:
> Hi Arthur,
> let me download the latest version of gem5 and try it.
>
> Do yo
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