Hi Mike,
I just tried it as well and that portion of the build seems to be
broken. Not many people use the shared library. Unfortunately, I'm not
going to have time to look into it for a while, but if you see what
older version you have that works and the current version you should be
able to
You could either add m5ops to your binary to do it
(http://www.gem5.org/M5ops [1]) or you would need to modify the running
scripts a little bit to to call m5.simulate()
m5.stats.dump()
m5.stats.reset()
Ali
On Wed, 21 Sep 2011 22:57:02 +0200,
farshad firouzi wrote:
Hello,
I re
Hi Ibrahim,
The checker CPU doesn't work at the moment. There have
been some changes to the memory system and underlying classes since the
checker was originally written and no one has gone back and made it work
again. It's something that many people have considered doing, but no one
has invest
See an email thread with the subject:
Re: Error while building Gem5
Simulator
>From last week.
Ali
On Fri, 23 Sep 2011 02:22:55 -0400,
shu wrote:
Hi all,
I am trying to compile gem5 in a cluster. The
cluster's compiler is gcc4.1.2.
So I install a gcc4.5 on my local
account and to co
>
>
> Hi
>
> Sorry for the delay in responding. I switched to gem5 development
> instead of gem5 stable and this BUS problem went away. However, I have
> new issues. I list them here :
>
> 1. When I boot ARM FS with the kernel,bootloader and file images
> available here : http://www.m5sim.org/D
On Sep 24, 2011, at 8:37 AM, Anirudh Sivaraman wrote:
> On Fri, Sep 23, 2011 at 10:57 PM, Ali Saidi wrote
>>
>> You need to make sure the board time is a realview PBX.
>
> Thanks for the response. However, I am still confused about where this
> needs to be m
Try using gem5 rather than the stable repository.
Ali
On Sep 23, 2011, at 2:52 PM, shu wrote:
> Thank you very much.
>
> I can compile now. I just downgrade the swig to version2.0.2
>
> But When I run the m5.opt, I got another error:
>
> ---
Why don't you try the config file in
http://www.gem5.org/dist/current/arm/arm-system-2011-08.tar.bz2
Ali
On Sep 24, 2011, at 12:14 PM, Anirudh Sivaraman wrote:
> On Sat, Sep 24, 2011 at 11:18 AM, Ali Saidi wrote:
>>
>> On Sep 24, 2011, at 8:37 AM, Anirudh Sivaraman w
The image needs some sort of partition table and this one works
perfectly fine.
Ali
Hi
I have a related question. I downloaded both the old and new versions
of the ARM binaries and disk images from http://www.gem5.org/Download
Once I extracted the tars, I cded to the disks directory and ran
On Mon, 26 Sep 2011 19:34:25 -0400, Anirudh Sivaraman
wrote:
On Mon, Sep 26, 2011 at 6:34 PM, Ali Saidi wrote:
The image needs some sort of partition table and this one works
perfectly
fine.
Hi
Thanks for the clarification. I ran the Android kernel ( built using
the config files you
Do you have a configs/common/cpu2000.py?
Ali
On Sep 27, 2011, at 6:02 AM, xxx wrote:
> Hi,
> Can anyone offer a document about how to run SPEC2000 or SPEC2006 on ARM_SE?
> I try to make it work by following the guide on the website
> (http://gem5.org/SPEC2000_benchmarks)
> for more than one
Don't use the DRAM memory. It should probably be deleted from the tree.
Just like the warning message says when the simulator starts:
> warn: This DRAM module has not been tested with the new memory system at all!
Ali
On Sep 28, 2011, at 9:28 PM, XIANGYU wrote:
> I want to have a detailed DRA
This is getting ridiculous. There are like 4 versions of SWIG that work now. We
really need to figure out why 2.0.4 is broken.
Ali
On Sep 28, 2011, at 8:31 PM, Digant wrote:
> ok thank you for quick reply,
> I have 1.3.40 also and I can install 2.0.3 , I ve checked SConstruct file but
> I didn
This needs to be relative of where this script lives... Unless it's in a
director under configs this isn't going to work.
Ali
On Sep 28, 2011, at 3:04 AM, xxx wrote:
>> m5.util.addToPath('../configs/common')
___
gem5-users mailing list
gem5-users@gem
It means that the memory isn't responding because the block is in another cache
and that cache will forward the block.
Ali
On Oct 12, 2011, at 3:42 AM, lorraine luna wrote:
> Hi!
> I modified CacheConfig.py such that I will have private l2 caches, the same
> number as the number of cores
> ***
You should be able to do it either way. With the classic memory system you
would just need to change the config scripts a little bit to setup the clusters
as you described. Someone else will have to describe how that can be done in
with the ruby memory system.
Ali
On Oct 11, 2011, at 11:44 AM,
Well, minimally you need an init binary. Any particular reason why you're
looking for a minimum? Seems easier to just use one of the prebuilt images.
Ali
On Oct 7, 2011, at 12:39 PM, Anirudh Sivaraman wrote:
> Hi
>
> I wanted to know what's the required minimum set of files and folders
> in t
Value speculation or issuing a load speculatively. The prior no, the latter yes
assuming you're using the o3 cpu.
Ali
On Sep 25, 2011, at 6:59 PM, xxx wrote:
> Hi,
> Is ARM_SE simulator support load speculation ?
>
> Thanks.
> Joshua
> ___
> gem5
On Oct 16, 2011, at 4:09 AM, MJose Díaz wrote:
> Hi
> I am new to gem5. I am sorry if questions are basic questions.
>
> Firstly, I would like to change some parameters as number of physical
> registers,
See O3CPU.py
> numbers of registers banks,
This isn't modeled in gem5
> simulation ti
84
> #16 0x773fe313 in PyEval_EvalFrameEx () from
> /usr/lib/libpython2.6.so.1.0
> #17 0x773ffd60 in PyEval_EvalCodeEx () from
> /usr/lib/libpython2.6.so.1.0
> #18 0x773fe0ab in PyEval_EvalFrameEx () from
> /usr/lib/libpython2.6.so.1.0
> #19 0x773fe9
For which architecture?
Ali
Sent from my ARM powered device
On Oct 18, 2011, at 3:44 PM, Adam Jacobvitz wrote:
> I'm trying to set up a custom ubuntu image to work with gem5. I got the image
> to load into gem5 and the OS set up, but upstart seems to choke during
> startup. I get to:
>
> N
Some ISAs (Alpha, ARM) encode special information in the lowest bits
of the current instruction address. You don't want these bits to be used
to calculate the address, but it's important that they're there for
instructions that might consume them.
Ali
On Wed, 19 Oct 2011
22:49:52 +0800, Xueha
t 20, 2011, at 5:56 AM, MJose Díaz wrote:
> Thank you
>
> With respect to number of physical registers: I've changed this value to 15.
> However, the NUM_INTREGS variable appears as 42 and I do not find where 42
> is assigned to NUM_INTREGS.
>
> Thank you in advance.
Events that are supposed to happen with the program counter is a certain value
(as opposed to an event when the simulated time is a certain value). It isn't
widely used, but ends up being used for things like emulating dprintk() inside
gem5.
Ali
On Oct 19, 2011, at 11:44 AM, Xuehan Xu wrote:
If the simulated system is running a program, you might not have a shell prompt
(because the benchmark is running in the foreground).
Ali
On Oct 19, 2011, at 8:00 AM, Adam Jacobvitz wrote:
> This is my command line output:
>
> gem5 Simulator System. http://gem5.org
> gem5 is copyrighted softw
There are some issues with gcc 4.6 and python 2.7 that break compilation. We're
trying to get these fixed, but in the mean time please use gcc 4.5 and python
2.6.
Ali
Sent from my ARM powered device
On Oct 28, 2011, at 9:08 PM, Digant wrote:
> I had the same error , try gcc-4.5 , I don't kn
Not really, although you could create some support for this. Another option is
m5threads, but it only works for some architectures.
Ali
On Oct 23, 2011, at 10:13 PM, Xuehan Xu wrote:
> Hi, all
> I saw that in SE mode, we can create a system with multiple CPUs and
> assign a different work
The model has been made more generic and there isn't an architecture specific
variant anymore. Anything architecture specific has been moved into the
src/arch// directory.
Ali
On Oct 21, 2011, at 10:47 PM, Xuehan Xu wrote:
> Dear Sirs:
>I'm trying to read the source code of O3CPU Mode
If you indeed compile it statically you shouldn't be seeing that error.
Ali
On Nov 2, 2011, at 10:39 PM, Chao Chen wrote:
> Hi,
>
> I am trying to compile eembc benchmarks to run on alpha in FS mode. I got
> the following error when runing the compiled exe files
>
> .A.exe: /lib/libc.so.6.1: v
The inorder CPU doesn't support full system yet. It's quiet close, but there
are a few outstanding issues.
Ali
On Nov 2, 2011, at 4:31 PM, shu wrote:
> Hi all,
>
> When I run gem5 with inorder cpu, I got a error message
>
>
> REAL SIMULATION
> info
Take a look at the PCEvent class and the objects that currently derive from it.
That seems like it will do what you're after.
Ali
On Nov 1, 2011, at 11:44 PM, Hongil Yoon wrote:
> Hi guys,
>
> Does Gem5 support magic break point like Gems?
>
> What I wanna do is to turn on a flag(bool type) o
There is some support for SMT in the o3 cpu, but it's not regularly used, so it
might have some rough edges.
Ali
On Oct 30, 2011, at 9:17 PM, Ankita (Garg) Goel wrote:
> Hi,
>
> I wanted to know if gem5 supports smt or hardware threads ?
>
> --
> Regards,
> Ankita
>
>
>
We'll need a gdb backtrace to have any idea what is going on, but a
good first step is to try the latest version of the development
repository (as opposed to the stable one which you're currently using).
Ali
On Wed, 9 Nov 2011 23:28:19 +0530, Meeran Mohideeen wrote:
Hi ALL
I am newbie to
You'll need to look at a gdb backtrace and see what is going on. I don't know that anyone has tried >16GB of DRAM, so it might take a little bit of work.
Ali
On Thu, 10 Nov 2011 01:05:45 +0900, Tae Jun Ham wrote:
Hello,
I tried running a simulation with 32GB physical memory and I got "Seg
Hi Anders,
That code has only been used with Alpha, but in theory
it could be used for other ISAs. The values come from a kernel with an
extra file that gives us some hints. Take a look at
http://repo.gem5.org/linux-patches/file/0ab58d9bd9a5/m5/m5struct.diff
Ali
On Wed, 9 Nov 2011 13:24:52
Do you have g++ installed? What happens if you run: g++ -dumpversion
?
Ali
On Tue, 8 Nov 2011 23:33:07 +0530, Meeran Mohideeen wrote:
HI,
When i try to compile gem5 in ubuntu10.10 using scons. I am
getting the following error.
meeran@ubuntu:~/gem5-stable-b9ba22cb23f2$
scons build/ALPH
You can add some code to to the setMiscReg() implementation that chages the
asid to print something out.
Ali
On Nov 11, 2011, at 3:47 PM, Charles Gala wrote:
> Thank you for replying to my post.
>
> Seeing the ASID would definitely be sufficient for what I am trying to do. I
> think I'd like
The brackets ([]) mean that the parameter is optional, but it's a parameter.
Specify one and it will dump in that many ticks, two and it will continue to
dump every however many ticks.
E.g.
m5 dumpstats 10 100
would dump stats in 10 ticks and then again every 100 ticks after that.
Ali
On No
Increase the size of the stack (you'll need to edit process.cc both in the sim
directory and in the arch directory.
Ali
On Nov 12, 2011, at 4:30 AM, Mahmood Naderan wrote:
> Hi,
> Previously I thought
>
> info: Increasing stack size by one page.
>
> is not important however with this fatal er
Is the latest swig actually broken? Is it our issue or swig's? If it's swig's
we should probably tell them, lest it get picked up by a major distro and be a
continuing issue for us.
Ali
On Nov 14, 2011, at 10:10 PM, Gabriel Michael Black wrote:
> gcc 4.6 problems should be fixed in the latest
It's probably still booting, it takes about an hour to boot android and give
you a splash screen.
Ali
On Nov 19, 2011, at 5:24 AM, yanke wrote:
> For the file system ARMv7a-Gingerbread-Android.SMP.mouse.nolock.img I attach
> a term to it. It gave the following output. I think it misses a init
--prog-interval= on the command line.
Ali
On Nov 20, 2011, at 3:57 AM, Mahmood Naderan wrote:
> Hi,
> I want to paste a message every 10M instructions so that I can see
> progress of simulation.
>
> To do that I wrote:
>
> void
> CPUProgressEvent::process()
> {
>Counter temp = cpu->totalIn
The python scripts are in complete control of the simulation, so you can do
anything like this that you want, you'll just have to write some code to do it
in configs/common/Simulation.py.
dump stats:
m5.stats.dump()
reset stats:
m5.stats.reset()
simulate some number of ticks:
m5.simulate()
sim
It works without issue. Are you using FS or SE?
The best way to do this is generally to recompile the program with a
m5chechkpoint instruct placed where detailed simulation should begin. You can
then restore from this checkpoint to run your simulation.
Ali
On Nov 23, 2011, at 12:21 PM, Rio
The prefetch instructions in the alpha ISA don't actually do anything. They're
ignored.
Ali
On Nov 20, 2011, at 11:57 PM, Hasina Khatoon wrote:
> What is the reason for this message being the output only when a
> prefetcher is put on in ALPHA_FS mode?
>
> Can anyone please explain?
>
> Thanks
There is a way, but it's not necessarily easy. It platform it's attached and
how it's setup there determines the mode. You'd have to hack on the kernel a
bit to make it work.
Thanks,
Ali
On Dec 9, 2011, at 9:42 AM, David Roberts wrote:
> Hi,
>
> From what I understand, the ARM ubuntu full-sy
Try re-compiling the palcode. A bug was fixed in it many years ago that seemed
to have a similar problem, but it might have never been added to the default
binary download.
Ali
On Nov 29, 2011, at 2:27 AM, rs l wrote:
> Dear all,
>
> I'm using the latest ALPHA_FS/gem5.opt simulator.
> I conf
I think a better approach is M5_VAR_USED on the offending variable.
Ali
On Tue, 13 Dec 2011 09:25:22 -0600 (CST), Nilay Vaish
wrote:
On Tue, 13 Dec 2011, Fabian Oboril wrote:
Hi guys,
I have recently updated my Ubuntu to version 11.10. I have now huge
problems with the integrated gcc 4.6
This issue is fixed now. The reason it wasn't caught before is people normally
use caches in timing mode and gem5 requires caches with the o3 cpu.
Ali
On Dec 14, 2011, at 6:45 PM, Anthony Gutierrez wrote:
> It seems as though a recent changeset has broken things. I have tried running
> the ful
You can add events like the following:
if
(kernelSymtab->findAddress("__udelay", addr)) {
uDelaySkipEvent =
new UDelayEvent(&pcEventQueue, "__udelay", fixFuncEventAddr(addr), 1000,
0);
}
This could be based on parameters and will work just fine if
you are interested in kernel events.
extern "C"?
Ali
On Thu, 15 Dec 2011 10:20:39 -0500, wrote:
When I tried to use m5_dump_stats and m5_reset_stats in my program,
the
functions are written in assembly which is only recognized by gcc,
not by
g++. So I cannot use these funcs when my source code is C++. I just
wonder
if someone c
M_FS/gem5.opt ./configs/examples/fs.py -b bbench
>>
>> -Tony
>>
>> On Sun, Nov 20, 2011 at 9:01 PM, yanke wrote:
>> ./build/ARM_FS/gem5.opt ./configs/examples/fs.py
>>
>>
>>
>> At 2011-11-20 22:14:28,"Anthony Gutierrez" wrote:
&
It's the PC advancing and the micro-pc advancing (for micro-coded instructions.
Ali
On Dec 19, 2011, at 10:49 AM, Mahmood Naderan wrote:
> (0x405bdd=>0x405be1).(0=>1)
> (0x405bdd=>0x405be1).(1=>2)
> (0x405bdd=>0x405be1).(2=>3)
> (0x405bdd=>0x405be1).(3=>4)
> (0x405be1=>0x405be4).(0=>1)
> (0x405be
It's pretty clear that the simulator could not open this file.
Did you download it? Is it in the path below? Is it readable by the user your
running gem5 with?
Ali
On Dec 21, 2011, at 12:57 AM, yanke wrote:
>
> /home/yanke/sde/gem5/system/arm-system-2011-08/disks/ARMv7a-Gingerbread-Android.
The ubuntu image is, "headless," that is to say there is no gui installed. You
would need to create an image with all those packages installed if you wanted
to use ubuntu. There are instructions on the wiki about creating a bootable
image.
-
As for the android image, you should be using
ARMv7a
but still get the same error.
>
> On the other hand, given my original intent of doing specific actions right
> after a full GUI boot, I am guessing I can still do that using the bbench
> disk image, but replacing the bbench rcS file with my own custom rcS file?
>
> Any help is
You'll need to modify the configuration files to create two difference CPUs.
There aren't command line parameters to do these sorts of things.
Ali
On Jan 2, 2012, at 3:49 AM, huangyongbing wrote:
> Hi all,
>
> Generally, if there are two CPUs on a CMP machine, both the CPUs are of the
> same
Just to highlight the most important bits of this email...
If
you've cloned the gem5 repository (not gem5-stable) you *must* do one of
the following.
The *easiest* is to just save any changes you currently
have outstanding, remove any patches you have in the patch queue, and
switch over to a
That's ok, but it would break if you had a different CPU model activated. The
better thing to do is something like:
class MyO3Cpu(DerivO3CPU)
issueToExecuteDelay = 2
decodeWidth = 4
…
and every where in Simulation.py replace DerivO3CPU with MyO3Cpu
Ali
On Jan 7, 2012,
Take a look at
util/m5/m5.c
Ali
On 09.01.2012 12:14, Ankita
(Garg) Goel wrote:
> Hi,
> The dumpstats routine is called from
within the booted OS in fs mode using the command "m5 dumpstats". There
are other similar commands like "m5 [resetstats|dumpresetstats|..]".
>
> Regards,
> Ankita
We don't support all syscalls, but you can implement the
functionality if you want. The getrlimitFunc is defined in
src/sim/syscall_emul.hh. Currently it supports reporting the stack size
and the data size. You can follow the template there to add whatever 7
is.
Ali
On 10.01.2012 18:05, Rio
Hi Jack,
People generally don't make checkpoints with the detailed CPU as the cache
state isn't saved, and thus you can't restore from the checkpoint (any dirty
lines would be thrown away). It would be possible to either checkpoint the
dirty state in the caches, or write back the dirty data int
If you do postreview -o the current applied patch will be sent.
Ali
Sent from my ARM powered device
On Jan 11, 2012, at 11:50 AM, Nilay Vaish wrote:
> Try hg qdiff. It will show you all the changes that are part of the patch and
> those are not yet part of it. After doing hg qref, all the c
The example below should work, but you'll need to call m5.stats.reset() as well.
Ali
On Jan 12, 2012, at 7:12 PM, 马君 wrote:
> As far as I know, prog_interval imply fixed ticks, how to dump by instructions
> Thanks
>
> 发件人: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] 代表
>
The assert needs to be removed (I think it is in the latest
repository). Don't run the debug version and it wil work.
Ali
On
13.01.2012 11:14, Manu Awasthi wrote:
> Hi,
> I am running m5.debug
2.0 for the ARM_FS configuration, using DRAMMemory in FSConfig.py. I am
using the vmlinux.arm.sm
Hmm.. the colorization doesn't do wonders for the readability, but
if you cat it it should help.
Thanks,
Ali
On 17.01.2012 10:48,
Paul Rosenfeld wrote:
> Oh, it turns out the value was cached and
didn't update when I fixed up my header. Deleting the entire build/
directory and re-running
I think the idea was marking the variable as used and thus disabling the unused
warning. I can see your argument however. If you're motivated to change it
everywhere I wouldn't object.
Ali
On Jan 18, 2012, at 1:32 PM, Paul Rosenfeld wrote:
> I was perusing the code and I stumbled on this lit
All reamed registered in the o3 cpus are converted into a single flat index
space: integer: float: miscellaneous. If you want to read them you'll need to
either undo this mapping. THis isn't architectural register N, but physical
register N that you're accessing.
Ali
On Jan 20, 2012, at 9:21
Hi Anders,
No clue. It looks like Nilay last edited that code 3 months ago. So maybe he
can shed some light on it. Is the problem reproducible in the checkpoints?
tickEvent is scheduled when the device is created and isn't ever de-scheduled,
so it should always have a positive value.
_when is
, but _when is only 18750, causing
the bad value.
> Just saving the _when value might work, but I think it
will just cause an event scheduled in the past error. But I will need to
test.
> / Anders
>
> On Sat, Jan 21, 2012 at 4:43 PM, Ali Saidi
wrote:
>
>> Hi Anders,
http://www.m5sim.org/Tutorials
On Jan 27, 2012, at 2:07 AM, Mahmood Naderan wrote:
> Hi,
> Seems that the ASPLOS08 presentation can not be reached from
> http://www.m5sim.org/ASPLOS_2008
>
> How can I find that?
> --
> // Naderan *Mahmood;
> ___
> gem5
What happens if you just run build/ARM_FS/gem5.fast
configs/example/fs.py -n 2?
You should be using the kernel named
vmlinux.arm.smp.fb.2.6.38.8 that is available in the arm full systems
file tarball.
Ali
On 02.02.2012 09:16, Tosiron wrote:
> Hi,
>
I've been struggling with getting mult
Hmm.. I'm very surprised this works.
The correct solution is to do
something like:
if test_sys.iobridge:
test_sys.iobridge.ranges.append(AddrRange(mem_size))
else:
#instaniate a bridge
A third option may be to just all the x86 bridge
something else ioapic_bridge and have two bridge
as working?
What's it doing now that's different that makes it not
> work? Why is
it doing it that way instead of the way that worked before?
>
> Gabe
>
> Quoting Ali Saidi :
>
>> Hmm.. I'm very surprised
this works. The correct solution is to do something like
chive.com/gem5-users@m5sim.org/msg05359.html
>
> On Thu, Feb 2, 2012 at 12:57 PM, Ali Saidi wrote:
> What happens if you just run build/ARM_FS/gem5.fast configs/example/fs.py -n
> 2?
>
> You should be using the kernel named vmlinux.arm.smp.fb.2.6.38.8 that is
> available
Hi Kirtka,
You're going to have to figure out why the KMI is getting that byte. I've never
seen that error before.
Ali
On Jan 22, 2012, at 6:38 AM, Kirtika Ruchandani wrote:
> Hi,
> Thanks for your response. I built and ran the revision you mentioned, but it
> aborts after some cycles -
>
>
What compiler are you using?
On 06.02.2012 14:21, Monobrata
Debnath wrote:
> I was trying to compile gem5 in ALPHA_FS mode. The
following error is
> encountered.
>
>
build/X86_FS/base/cprintf_formats.hh:202: error: ambiguous overload
>
for 'operator
http://m5sim.org/cgi-bin/mailman/listinfo
On Feb 8, 2012, at 8:19 AM, Knute Lingaard wrote:
> Also, I'm concerned that I'm touching on a use case that isn't supported
> (based on your statement "I don't ever use that functionality"). Is
> check-pointing a supported use case for the SE mode of simulation?
It is, Gabe just doesn't use i
t works
now.
> You mentioned my kernel. I'm using the android disk image
(distributed with bbench), which is why I'm using the
vmlinux.smp.mouse.arm kernel. I tried using the other one, but it just
hangs, and doesn't seem to work. Is that fine?
>
> On Fri, Feb 3, 2012
at 8:36 PM
Hi Paul,
Yes, in SE mode, it's just faked as a pipeline flush (in
the simple CPU model then pretty much nothing happens). It should be
reasonably easy to change the model to delay some number of ns on a TLB
miss, but you'll get the best results by running in fs mode.
Ali
On
09.02.2012 01:0
n the instruction, or to do something where they all get
translated together using a new fault?
>
> On Thu, Feb 9, 2012 at
10:16 AM, Ali Saidi wrote:
>
>> Hi Paul,
>>
>>
Yes, in SE mode, it's just faked as a pipeline flush (in the simple CPU
model then pretty much
:
> Well that doesn't sound like fun.
Perhaps I'll look at ARM as a potential target.
>
> On Thu, Feb 9,
2012 at 11:39 AM, Ali Saidi wrote:
>
>> It's
possible with Alpha, but it would take some work. You'd need to "take" a
fault up to times and
This should be fixed with the change Gabe committed.
Ali
On Feb 9, 2012, at 10:15 PM, Heba Saadeldeen wrote:
> Hi,
>
> I am trying fast forwarding simulation but I am still having trouble, I am
> just running a test program
>
> build/ALPHA/gem5.opt configs/example/se.py -c tests/test-progs/h
Thanks Robin,
We'll get this committed.
Ali
On Feb 9, 2012, at 4:23 PM, robin wrote:
> build/ALPHA_SE/gem5.opt ./configs/splash2/run.py --benchmark FFT
> --rootdir="./v1-splash-alpha/splash2/codes" -n4
>
> while running run.py encountered the following error -
>
> panic: System port on syste
Hi Heba,
There are three possibilities:
1) The program requires correct FP exception behavior to work. This usually
isn't the case and I don't think we handle arithmatic faults in SE mode
correctly for any ISA.
2) There is a bug with our Alpha support that make making you hit his issue
3) There
It's probably still running. Depending on what input set you're using it could
take a very long time to simulate a spec 2006 benchmark. You'll need to reduce
your input set, do or do some kind of sampling.
Ali
On Feb 12, 2012, at 4:18 PM, z...@uwaterloo.ca wrote:
> Hi everyone,
>
> I am tryi
gt; of this, sorry if it seem like a trivial question.
>
> Also I doubt it takes that long to run. When I just execute the binary by
> itself in the command line, it takes less than 5 minutes to finish executing.
> Would it really take that long to run such a small program in gem5?
&g
You need to hook-up the system call in
src/arch/x86/linux/syscalls.cc and ultimately you'll need to look at the
implementation of the ioctl call in src/sim/syscall_emul.* and see if it
does something sensible for what this benchmark is trying to use it for.
Most of the time it's just the c libra
Since the model was written the driver has made use of features in
the adapter that aren't implemented. You can use the the NIC in e1000
mode and that should work or you can try to implement the missing
features.
Ali
On 13.02.2012 13:08, Pritha Ghoshal wrote:
> Hi,
>
> I am trying to run
On 13.02.2012 14:09, Pritha Ghoshal wrote:
> Hi Ali,
>
> Thanks
for your reply. I saw that you had made use of the NIC in the 2009 ISCA
> paper, so I assumed it was working, I guess the drivers have changed
from then.
>
> Do you know which features are missing and need to be
implemented?
Then the best thing to is use tracediff to see where the programs diverge with
512k and 2MB. Have you made any changes to the simulator?
Ali
Sent from my ARM powered mobile device
On Feb 14, 2012, at 12:06 AM, Mahmood Naderan wrote:
> Thing is, a benchmark works fine with a 512kB L2. However
Hi Patrick,
That is great, please put in on the wiki.
Thanks,
Ali
On 14.02.2012 12:32, David Brenner wrote:
> This is very
useful. I made a similar figure in my notebook when I
> started looking
at the m5 code. Would you mind uploading it to the
> gem5 wiki as
well?
>
> On Tue, Feb 14
HI Teng,
It depends on where you are. Internally the CPU models
have different ways of mapping registers. From an external point of view
this is wrapped up in a ThreadContext (tc). Nominally, you can call
tc->readIntReg() and should get the right thing.
Ali
On
14.02.2012 14:32, Teng Lu wro
On 16.02.2012 10:52, Pritha Ghoshal wrote:
>> Hi Pritha, I don't
know why you're seeing that error, if you just use IGbE_e1000() I
>
>
think it should work. That said, all of the upheaval in the memory
system over
> the last few weeks might have broken something. The first
trick is to unders
That depends on how/what you're running. If your booting linux you can just
execute m5 dumpresetstats before running
your application. If you want to do a similar thing with sys call emulation,
you'll need to do some hacking on the run loop in Simulation.py to only run for
a number of ticks a
delete your build directory and recompile. Sometimes scons seems to miss a
dependency.
Ali
On Feb 17, 2012, at 7:02 AM, Mahmood Naderan wrote:
> Hi,
> Another problem fter updating to the latest revision:
>
>
> Using saved variables file /home/mahmood/gem5/build/variables/X86_SE
> NameError:
If you get an execution trace right before this happens that might shed some
light on it. Tracking how the address that is being used is assembled by the
cpu is a good start.
Nothing jumps out at me though, so I'm pretty confused why I don't see the
problem and you do.
Ali
On Feb 16, 2012,
You can't if the ISA you're using does any kind of micro-coding. The easiest
thing is to just start the trace and throw away the first 1M lines. A slightly
more complicated method is to set a max_insts_any_thread to 1M on the CPU and
modify the simulation script to execute something like
m5.deb
modifying the Simulation.py
> using a loop of m5.simulate(), m5.stats.reset() and m5.stats.dump().
>
> On Sun, Feb 19, 2012 at 7:41 AM, Ali Saidi wrote:
> That depends on how/what you're running. If your booting linux you can just
> execute m5 dumpresetstats before running
>
Some instructions are micro-coded, so each instruction can correspond to
multiple micro-ops. In the latest development repository we make this
distinction clear by having stats called opsComittted and instCommitted.
Ali
On Feb 19, 2012, at 3:02 PM, z...@uwaterloo.ca wrote:
> Hi,
>
> I am runn
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