To my knowledge running big endian binaries hasn't been tried. It might work,
but clearly there are some issues. Most notability is that in SE mode the
endianess is compiled into the simulator. You'll probably get a bit further if
you change LittleEndianGuest to BigEndianGuest is src/arch/arm/is
To use a the tlb (and have table walks) you would need to create a complete
page table. While doable, FS mode provides this if you want to use it.
Ali
On Aug 4, 2013, at 11:41 PM, GE ZHIGUO wrote:
> Hi,
> I found that the TLB implementation in SE mode is much different from
> that in fu
SE cannot support
> page fault if I am not wrong.
> But as you said, we can create a complete page table to handle this issue.
> Apart from this, are there other
> issues we need to handle?
>
> Regards,
> Zhiguo
>
>
> From: gem5-users-boun...@gem5.org [mailto:gem5-u
p Linux for some hardware features
> such as SMT.
> I am not sure which one is easier, SMT/SE with TLB or SMT/FS.
>
> Thanks!
>
> Zhiguo
>
> From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
> Behalf Of Ali Saidi
> Sent: Monday, Aug
Hi Yongbing,
Would you put a link to these on the gem5.org web site?
Thanks for providing everyone with these!
Ali
On Aug 22, 2013, at 7:46 AM, huangyongbing wrote:
> Hi all,
>
> I have gathered 11 Android applications as a benchmark suite called
> AsimBench, which cover several
Hi Hao,
There isn't any mechanism to free pages. Typically benchmarks run in SE mode
don't free and re-allocate a lot of memory, so this works reasonable well, but
ideally we would maintain a memory pool and allocate from it.
Thanks,
Ali
On Aug 22, 2013, at 4:16 AM, Hao Wang wrote:
> Hi,
>
What version of gem5 and what architecture/benchmark/os are you running?
You should be able to make a checkpoint with 1, 2, or 4 cores (or as many as
the particular system/platform supports). Booting without caches should work
just as well as booting with caches.
You should create a checkpoint
restore it, There are insts being
> executed, but I cannot see anything new from frame buffer if I use
> "--frame-capture". Any suggestion? Thanks
>
> Xiangyang
>
>
> On Tue, Sep 3, 2013 at 10:26 PM, Ali Saidi wrote:
> What version of gem5 and what architectu
take a couple of days.
Ali
On Sep 3, 2013, at 10:35 PM, Xiangyang Guo wrote:
> I restore into "--cpu-type=detailed", and I think I'm using development
> branch of gem5, I downloaded it about 3 months ago. Thanks
>
>
> On Tue, Sep 3, 2013 at 11:32 PM, Ali Sa
I think I've found a solution to this, I'll try and post a patch in the next
couple of days.
Ali
On Sep 7, 2013, at 10:51 AM, Ali Saidi wrote:
> I think I've found a fix for this. I'll try to post a patch in the next
> couple of days.
>
> Thanks,
>
take a look at the m5threads library that is gem5.org. It can be use to compile
simple pthreads code and run it on SE mode in gem5, although I'm not sure how
ALPHA support works.
Ali
On Sep 18, 2013, at 11:55 AM, Xiaowen Wu wrote:
> Hi All,
>
> I want to run a multi-threaded program on GEM5
ldr.w is a ldd that is encoded as a thumb2 instruction.
Ali
On Sep 17, 2013, at 10:46 AM, Jianghao wrote:
> From benchmark instruction trace on ARM architecture, there are following
> load instructions
> ldr
> ldr.w
> ldrb.w
>
> For ldr, I assume it will load word by default, so what's meaning
Hi Xiangyang,
The code is question is on the review board (http://reviews.gem5.org/r/2026/)
and will be committed shortly.
Thanks,
Ali
On Sep 25, 2013, at 11:12 PM, Xiangyang Guo wrote:
> Hi, all,
>
> from last year's user work shop, I see there is a software Streamline for
> Gem5. So I che
Hi Zhiguo,
There are two concepts here, cache states and the state of a exclusive monitor
(that checks if the cache line has been written since it was put in the
monitor) .While these concepts can be joined, they don't need to be.
So, you could probably add the NeedsExclusive attribute and it
n enter to
the critical section if spin lock is implemented through
loadlinked/storecontitional.
>
> There might be some bugs in
store-conditional logic or implementation in GEM5.
>
> Regards,
>
>
Zhiguo
>
> FROM: gem5-users-boun...@gem5.org
[mailto:gem5-users-boun..
It's un-usual that pkt->getAddr() and pkt->req->getVaddr() would be the same
after translation is complete. The latter will have the virtual address while
the latter will have the physical address. As the packet move down the
hierarchy it will be further modified to by block aligned, etc.
Ali
getAddr() will give us the
> Physical Address, pkt->req->getPaddr() should of course give us Physical
> address, but for L2, the two address (several most right bits)are different,
> but for L1, they are same. Could you help me about this? Thanks a lot.
>
>
> On M
I set of bmps is created in the output directory. Any image viewer should be
able to read them.
Ali
On Oct 9, 2013, at 10:38 PM, huangyongbing wrote:
> Hi all,
>
> I collect a collection of frame buffers using the parameter
> –frame-capture. But how can I view the output of these f
It should be fixed in the dev repository in the last couple of days.
Ali
On Oct 13, 2013, at 8:00 PM, Yuan Yao wrote:
> Dear all,
>
> I am experiencing the same problem to the thread posted before
> http://www.mail-archive.com/gem5-users@gem5.org/msg08426.html
> The panic shows during the "fre
The value is written to the cache which notices it's non-cacheable and
passes it to the next level of the memory system. This continues until
the request reaches the memory it's destined for.
Ali
On 23.10.2013 15:27, Xiangyang Guo wrote:
> Hi,
>
> can anyone tell me how gem5 handles the
Hi Guru,
Can you compile the m5 binary in the util/m5 directory, but in on the disk
image and check if it works? Perhaps you’re using an older version of the
binary because it does work for me and the addresses you print below aren’t
valid addresses for ARM.
Thanks,
Ali
On Oct 29, 2013, at 4
Hi,
It looks like you’ve got a couple of conflicting versions of python. Was scons
installed using the version of python that you have in your path? See the
following for more information:
http://stackoverflow.com/questions/13194308/importerror-cannot-import-name-urandom
Ali
On Nov 4, 2013, at
You need to change the ISA files as well. Search for an existing pseudo inst in
src/arch/arm/isa/
Ali
On Nov 11, 2013, at 9:10 AM, JIN MIN KIM wrote:
> Hi all,
>
> I'm working on extending the ARM ISA by adding pseudo instructions.
> I choose 0x56 as the opcode.
> I've already added new opera
We no longer support Python 2.4. It’s very old at this point and you should
upgrade if you’re able.
Thanks,
Ali
On Nov 8, 2013, at 12:05 AM, Chetan Patil wrote:
> Hi Peng,
>
> On Thu, Nov 7, 2013 at 11:58 PM, Peng Wei wrote:
> I found that new version of gem5 cannot run on python 2.4 because
Why are you not able to run parsec on ARM?
Ali
On 25.11.2013 20:28, Vidyacharana Honnakatte Ramesh wrote:
> Hello all,
>
> I am considering classic memory system for ARM for my project. However, I am
> not able to run PARSEC for ARM. Hence, I want to use X86 classic memory FS
> system w
Is it possible that cpu1 was asleep. You need to look at what is going on with
the core right before the checkpoint happens and then look at what happens when
the checkpoint is restored. Does it start fetching or does it do nothing at
all? etc.
Thanks,
Ali
On Nov 19, 2013, at 1:36 PM, Tayyar R
You can create a dummy branch predictor that always returns not-taken.
Ali
On Nov 20, 2013, at 9:59 PM, Vanchinathan Venkataramani
wrote:
> I would like to know if there is a way to disable branch predictor in O3 CPU
> model for ARM.
>
> Thanks
> V Vanchi
>
> ___
That stat is for SMT-style cores, not MT.
Ali
On Nov 26, 2013, at 7:45 AM, Mahmood Naderan wrote:
> Hi,
> Looking in to code cpu.cc, I see
>
> ipc
> .name(name() + ".ipc")
> .desc("IPC: Instructions Per Cycle")
> .precision(6);
> ipc = committedInsts / numCycle
Or you can increase the open file limit in your shell.
Ali
On Nov 27, 2013, at 10:12 AM, biswabandan panda wrote:
> m5.disableAllListeners()
>
> put the above line in your fs.py
>
>
> On Wed, Nov 27, 2013 at 8:38 PM, יואב אורן wrote:
> Hi,
>
> I'm running dedup from Parsec on a 64 cores ar
We don’t properly handle all the arithmetic faults (e.g. divide by 0) in gem5
because correct code normally doesn’t do that. There are two options. (1)
xanalcbmk requires faulting handling (2) a bug somewhere else in gem5 is
causing a value to be 0 when it otherwise shouldn’t be.
Thanks,
Ali
O
Take a look at the configuration files in config/ You can see the incantation
of different functional units and them being assembled into a functional unit
pool.
Thanks,
ali
On Dec 14, 2013, at 3:36 AM, Yuhang Liu <168liuyuh...@163.com> wrote:
> Could any one tell me how to configure the numbe
You could put Cache parameters on whatever SimObject you to get a pointer to
and assign the objects to those parameters in your configuration file.
Ali
On Dec 13, 2013, at 8:39 PM, Sudarshan wrote:
> Hi,
>
> We were trying to access the L1(I and D) and L2 cache stats by passing
> pointers to
You could solve the problem with a script in the simulated system that will
call m5 (the util/m5/ binary) exit after all the process that you’ve run
terminate.
Ali
On Dec 10, 2013, at 12:32 AM, Ranga, L Udaya wrote:
> Hi,
>
> I’m trying to write an application and run it on multiple ARM cor
Do you have a /etc/hosts file with 127.0.0.1 in it?
Ali
On Jan 4, 2014, at 12:53 PM, Zohreh Naghibi wrote:
> I have bound the server to 127.0.0.1. I have got this error:
>
> UDP server - socket() is OK
> UDP server - bind() error: Cannot assign requested address
> UDP Client - socket() is OK!
>
Hi Peng,
It looks like you’re creating a checkpoint and then existing. The script that
you are using is read into the simulated filesystem early on, so even if you
changed it after you restored the simulation, you’re not getting what you
expect. The script has already been loaded and the exit is
I don’t really understand what you’re saying here. The stats you’re getting
should be from when the simulation was started/restored until the exit unless
you’ve configured the script to dump/reset stats more frequently.
Ali
On Dec 27, 2013, at 1:38 PM, Chetan Patil wrote:
> Hi Ali,
>
localhost
> ::1 localhost
>
>
>
> On Sat, Jan 4, 2014 at 11:38 AM, Ali Saidi wrote:
> Do you have a /etc/hosts file with 127.0.0.1 in it? Ali
>
> On Jan 4, 2014, at 12:53 PM, Zohreh Naghibi wrote:
>
>> I have bound the server to 127.0.0.1. I have go
Thanks for reporting the issue Patrick. I upgraded the wiki last night
the address some recent security issues with mediawiki and thought it
was working correctly, but obviously not. It looks like an extension to
mediawiki was to blame and fixing that fixed the issue. Please let me
know if you e
I'd allocate a variable to put rpns() in and then see what happens.
rpns() is returning a 64-bit int in r0, and r1 and perhaps when it's
used with the variation printf something is going wrong in the compiler.
Also, what is the compiler actually emitting before that printf in your
code if you di
However you want to think about it it's possible to always get two
blocks at one level less at others, but there are many problems you're
going to have to consider. It will take some connected development to
make this work.
Ali
On 27.03.2014 11:35, QI JIA wrote:
> Hi all,
>
> I am new to
Not presently, but it's certainly a feature that has been desired.
I don't think it would be too hard to create a print/no-print flag for
each simobject and have it not print it's stats if it's set.
Ali
On 31.03.2014 05:48, senni sophiane wrote:
> Hi,
>
> Is it possible to enable stats
It doesn't. Its possible that a micro-op in the middle of a macro-op
could fault. In all these squash cases all instructions/micro-ops
preceding it in the pipeline will get thrown out, so everything with a
larger sequence number has to go. In the case of async things like
interrupts, the CPU kee
If you want to do this you really shouldn't be fast-forwarding but
instead should make a gem5 hooks library for parsec that emits the gem5
checkpoint m5op.
See: http://www.cs.utexas.edu/~parsec_m5/TR-09-32.pdf
Ali
On 03.04.2014 11:08, Naranjo Carmona, Alberto Javier wrote:
> Hi everyone,
Hi Everyone,
I’d like to announce the availability of ARMv8 support in gem5. The code is now
available in the gem5 development repository (http://repo.gem5.org/gem5). The
current release supports running AArch64 code in both full-system and sys call
emulation mode as well as preserving ARMv7 su
Yes, if you have a spin lock in some code, it's highly likely that a
faster core will spin for more instructions on that lock and therefore
the number if instructions will increase somewhat proportional to
frequency.
Ali
On 11.04.2014 10:29, Heba Khdr wrote:
> The number of committed instr
You can implement a parsec hook library with the m5op (E.g. m5 checkpoint) and
you’ll get the tick when the checkpoint is created.
Ali
On Apr 17, 2014, at 10:56 PM, Seyedhamidreza Motaman
wrote:
> Hello All,
>
> I would really appreciate if someone answer my question. I really need that.
> H
you can’t do it from gem5 without modifying the simulator code, however since
there are multiple sections of stats being written to the same file, you could
easily post-process it into multiple files.
Thanks,
Ali
On Apr 17, 2014, at 1:25 PM, Kuk-Hwan Kim wrote:
>
> Dear Gem5 community,
>
>
The request objects contain information like contextId or master Id that could
be used to determine where this request came from. This along with modifying
the replacement policy to select victims only from the portion of the cache
belonging to that core should do the trick.
Ali
On Apr 17, 201
On Apr 17, 2014, at 3:36 AM, Kuk-Hwan Kim wrote:
>
> Dear Gem5 community,
>
> I have simple two questions.
>
> 1. Do we have gem5 models which is similar to Cortex-M3 core + on-chip SRAM
> + on-chip flash? If not, what would be the most efficient building out of
> currently available compon
You need to know what the rcS script you’ve passed gem5 is doing and if it’s
reseting the stats at some point or dumping them (or both). One stats file can
have multiple different dumps in it.
Ali
On Apr 15, 2014, at 5:15 PM, Kuk-Hwan Kim wrote:
>
>
> Dear Gem5 Community members,
>
> I am
There isn’t any delay for a TLB hit as you mention.
Depending on what you configure your delays for the i and d cache, you could
assume that it’s access is overlapped with the cache access.
At this point there isn’t a way to configure a delay, but that functionality
could be added since transla
tick number?
>
> Regards,
> Hamid
>
>
> On Fri, Apr 18, 2014 at 10:07 AM, Ali Saidi wrote:
> You can implement a parsec hook library with the m5op (E.g. m5 checkpoint)
> and you’ll get the tick when the checkpoint is created.
> Ali
>
> On Apr 17, 2014,
FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> # THEORY OF LIABILITY, WHETHER IN CON
It’s very possible there is a bug here and a place where the idle vs. not-idle
isn’t handled. When the cpu goes idle it subtracts 1 from a variable and when
it resumes it adds one. If one subtraction is missing it will end up being >=2
which is the cause of the issue. You should be able to put s
On Apr 21, 2014, at 12:10 PM, Kuk-Hwan Kim
wrote:
>
> Dear Gem5 Communities,
>
> Here is the first few lines of stats.txt. While I am interpretating the
> results, I came across several questions as follows. If you can share
> knowleged on how to interpret these paraemters or any insight on
pin down
> this bug in the large amount of source files?
>
> -- Forwarded message ------
> From: Ali Saidi
> To: gem5 users mailing list
> Cc:
> Date: Sun, 20 Apr 2014 12:05:18 -0500
> Subject: Re: [gem5-users] Negative CPU not_idle_fraction
> It’s very poss
At first glance I think a solution would be to restrict the number of
mshrs that can be used for prefetches to some number that is less than
the total number of mshrs in the system. I think that will solve your
issue and it sounds like a reasonable approach.
Ali
On 22.04.2014 12:15, Srinivas
There hasn’t been any issue with the website as far as I’m aware.
http://www.downforeveryoneorjustme.com/gem5.org
On Apr 24, 2014, at 6:48 PM, Moslem Didehban wrote:
> Hi all,
> I want to obtain some general information about gem5 simulator, but gem5.org
> is unavailable for several days. Doe
Yes, you can create a disk image with dd and the partition in with fdisk and
format it with mkfs.ext3.
Googling turned up this which seems to be a good example:
https://wiki.archlinux.org/index.php/Creating_Arch_Linux_disk_image
Ali
On Apr 29, 2014, at 1:00 PM, Fernando Endo wrote:
> Hello,
>
You’ll need to use FS mode and you can ask the kernel like you would on a real
system.
Ali
On Apr 30, 2014, at 6:16 PM, Gautam Dhanabalan wrote:
> Hi,
>
> I wish to measure the number of page faults (minor and major faults) that
> occur when running SPEC benchmarks on ARM in SE or FS mode. I
Is this our bug, or do we need to inform the swig guys ?
Ali
On Jul 21, 2011, at 7:17 PM, Gabriel Michael Black wrote:
> While trying to get gcc 4.6.0 working, I found that 2.0.4 introduced a bug
> that prevented some things from compiling. It produced errors that were
> different from yours,
Int alu accesses is counting every register that has at least one integer
operand.
Ali
On Jul 21, 2011, at 5:40 AM, Iordan Alexandru wrote:
>
> Hello
>
> I am using gem5 to run a MP full-system simulation with Alpha. I am
> interested
> in profiling some applications in terms of instructio
of INT instructions (total_INT =
> system.switch_cpus0.iq.FU_type_0::IntAlu +
> system.switch_cpus0.iq.FU_type_0::IntMult +
> system.switch_cpus0.iq.FU_type_0::IntDiv). Why is this happening? Should I
> use
> another counter for total_INT ?
>
>
>
>
> ---
You need to open another terminal and run the m5term application in there. The
terminal that gem5 is running is just displaying warnings and other such
information.
Ali
On Jul 23, 2011, at 2:27 AM, Kun Lu wrote:
> To the question:
> Do you see any output from the simulator telling you it's expe
The atomic and timing CPUs count instruction in slightly different ways.
Ali
On Jul 25, 2011, at 2:36 PM, xxx wrote:
> Hi,
> I run a benchmark (openjpeg) on ARM_SE, with two kinds of configurations.
>
> The first configuration is as the following:
> ./build/ARM_SE/gem5.opt configs/example/
There ar various issues with the prefetcher connected to the l2 bus. I would'n
recommend using it an this time.
Ali
On Jul 29, 2011, at 11:04 PM, Hasina Khatoon wrote:
> I have installed the precompiled downloaded image from PARSEC website. When I
> run the following configuration, the benchma
If you use the latest development repository, I don't think this is an issue.
Ali
On Jul 29, 2011, at 3:02 AM, Fu Bin-zhang wrote:
> Hi all,
>
> I got an error when i compiled the gem5. I find that there is a
> discussion about this problem, but i cannot access this webpage maybe
> due to the C
HI,
It is possible to run android on gem5. It works juts fine, however you need an
android kernel, and filesystem. I'll try to post an android kernel config file
latter this week, but you'll need to build the filesystem yourself or find one
that is prebuilt. This is probably a pretty good start
Hi Satya,
Does the code run correctly on a real ARM system? Normally this issue is caused
by an actual problem with the binary or perhaps it's using a syscall that isn't
particular well tested and there is a problem there. You can use the statetrace
program in the util directory to compare exe
Depending on which architecture your running some of them store os
thread/pid/asid information in some registers. However, for something like
parsec, I doubt the threads are really moving so contextId (which is the core
number the thread is running on) is probably sufficient.
Aii
On Aug 5, 2
On Mon, 8 Aug 2011 12:56:10 -0700, nathan binkert
wrote:
If you can provide me the diff, that would be great!
This diff doesn't give you too much, but I started by creating a
qcow_compat.cc and qcow_compat.hh in addition to sucking in a few
files from qemu that do the actual implementation. B
You can't checkpoint the simulation with caches enabled. Any dirty
state in the caches isn't saved in the checkpoint.
Ali
On Tue, 9 Aug
2011 03:29:47 -0700 (PDT), Iordan Alexandru wrote:
Hello
I have
been having problems using the checkpoint feature in GEM5. I tried to
run a very simple
there no way to get a valid checkpoint in a simulation with caches
> enabled? Is there nothing that I can do (hack)?
>
> Alexandru
>
> From: Ali Saidi
> To: Iordan Alexandru ; gem5 users mailing list
>
> Sent: Tuesday, August 9, 2011 9:31 PM
> Subject: Re: [gem5
The kernel itself can't actually cause two devices in the memory system to
conflict. The platform you're trying to simulate only has 256MB of contineous
space starting at address 0. I believe you're trying to give the system more
memory that that.
Ali
On Aug 11, 2011, at 6:37 AM, 이동열 wrote:
>
switch_cpus is the O3 CPU.
Ali
On Aug 14, 2011, at 8:47 AM, Mahmood Naderan wrote:
> Hi
> With this command:
> build/X86_SE/m5.opt configs/example/cmp.py --caches --l2cache
> --l2cache --l2_size=2MB -d --fast-forward=1000 --maxinsts=1000
> -b bzip2
>
> I see these statistics:
>
> syst
You'd need to look carefully at what you're actually seeing in the cache. If
the cache tries to send a packet multiple times, it might you'll see multiple
traces of the same request. You'll also see ReadEx requests go out of the L2.
Ali
On Aug 14, 2011, at 5:12 PM, Dawei Wang wrote:
> Hello, e
The '-b' flag is only supported for certain architectures with certain
disk images. Only the ones with ARM in the name are supported with ARM.
You'll need to put together you're own workloads by using the readfile
command and creating disk images with your benchmarks of interest.
Ali
On Mon,
The script makes disk images (files that contain both a disk partition and a
partition table. If you use a .ext2 file gem5 expects it to just be a ext2 disk
image without the partition table. You'll want the prior not the latter and to
name it with a .img extension.
That will use a a compact f
one booted fine. Is there something that I am missing?
Thanks,
Brian
On Mon, Aug 15, 2011 at 6:07 PM, Ali Saidi wrote:
The script makes disk images (files that contain both a disk partition
and a partition table. If you use a .ext2 file gem5 expects it to just
be a ext2 disk image without the
Hi Navid,
Hav you made any changes to the simulator? it looks like you're using an older
version (based on the output). Could you try the latest code? Also, what
happens if you just restore the simulation to the atomic cpu (instead of the o3
one), does it work?
Ali
On Aug 16, 2011, at 4:34
Hi Rick,
I just committed a fix that addresses an issue I found
with newer kernels and our ide disk, but I haven't seen this one. It's
possible that they're related, so you might want to try it.
Ali
On
Fri, 19 Aug 2011 11:03:39 -0700, Richard Strong wrote:
Hi all,
I
was doing an exper
quot;switch_cpu". For example there are
>
> system.cpu.icache
> system.cpu.dcache
>
> but there is no similar parameter for system.switch_cpus
>
> Can you elaborate on that?
>
> On 8/14/11, Ali Saidi wrote:
>> switch_cpus is the O3 CPU.
>>
>> Al
Looks like the O3 CPU wasn't compiled into the simulator. Try removing the
build directory and re-compiling.
Ali
On Aug 21, 2011, at 3:50 AM, Mahmood Naderan wrote:
> Hi
> With the latest revision, I don't know why I cannot resume from the
> checkpoint.
>
> command line: build/X86_FS/m5.opt c
Most instructions that are branches are marked with the isControl or
isCond/UncondBranch flags. In some cases this isn't done because the
instructions are rather rare and using them as branches is deprecated.
POP and other similar LDM like instructions are created by the MacroMemOp
constructor
Most?
Ali
On Aug 22, 2011, at 11:35 AM, Richard Strong wrote:
> Updating gem5 to the current version appears to have removed most of the
> errors. Thanks for the tip.
>
> Best,
> -Rick
>
> On Fri, Aug 19, 2011 at 3:33 PM, Ali Saidi wrote:
> Hi Rick,
>
&g
I don't really understand what you mean by packages, but you'll probably want
to update to the latest version of gem5 as there are lots of prefetcher fixes
that have recently been committed.
Ali
On Aug 22, 2011, at 4:30 PM, Jorge Perez wrote:
> Hello,
> I am running the last stable version of g
You'll need to do something like add a in_usr_mode field to the Request objects
and then check that in the L2 cache.
Ali
On Aug 22, 2011, at 12:06 PM, biswabandan panda wrote:
> Hey,
>I want to track the accesses generated to L2 cache because of OS code
> and not the application in ALP
With the output you provided it's impossible to know what the problem is. I
would suggest recreating the image again with the gem5img.py script. The output
below doesn't show any partitions being recognized in the image.
Ali
On Aug 22, 2011, at 9:55 AM, Nilanjan Goswami wrote:
> Hi All,
>
> I
Hi Dibakar,
You'll need to just make something up that works and provides enough bits in
each interrupt register to support 128 cores. There is no magic formula. You'll
also need to make the complimentary changes to the kernel, palcode, and
src/dev/alpha/(backdoor|tsunami_cchip).*.
Ali
On A
Hi Anirudh,
It can, but you'll need to build an android file system and kernel. The
bootloader in available in arm-system tarball on the download page, but if
you're having trouble building the bootloader you're going to have a lot of
trouble building android and a kernel. Within the next coupl
25, 2011 at 12:20 AM, Ali Saidi wrote:
>> Hi Anirudh,
>>
>> It can, but you'll need to build an android file system and kernel. The
>> bootloader in available in arm-system tarball on the download page, but if
>> you're having trouble building the boot
The Ubuntu image is running upstart and many applications at startup that the
tiny image does not. It can take 20 minutes to reach a prompt.
Ali
On Aug 31, 2011, at 4:54 AM, IC wrote:
> Hello ,
>
> Because the ARM image from gem5 download page is small, I try to build a new
> big one.
>
> I
Looks like you didn't compile m5op_.S and link it... I'm not sure
if you're getting an error with that the c++ compiler at all. The only possible
reason some c++ name mangling, but you can resolve that my wrapping m5op.h with
extern "C" { .. }.
Ali
On Aug 31, 2011, at 1:35 PM, shu wrote:
There are several places in the code where we assume the max stack for a
program can only be 8MB. If in fact bzip2 is creating a lager stack then this
you'd need to update those places (one is where the fatal() you mention below,
another is in src/arch/alpha/process.cc) with a larger stack.
Ali
It should be possible to do something like call readfile from a script that was
created with readfile. You'll just need to do a little experimentation with
what works and what doesn't.
Ali
On Sep 15, 2011, at 2:57 AM, huangyongbing wrote:
> I also met the same problem. If I want to do large sc
Something like cpu->readIntReg(renamed_reg);
Ali
On Thu, 15 Sep
2011 14:44:59 -0400, Edward Kim wrote:
Hi
I want to look into the
register value when register is ready in rename stage.
What can I do for
it?
Specifically, I want to check the register value at line number 1022
in file src/
You'll have to run gdb and see what you can find.
Ali
On Thu, 15 Sep 2011 18:38:30 +0430, Mahmood Naderan
wrote:
Hi
I want to resume from a checkpoint in ALPHA_FS mode with this command
build/ALPHA_FS/m5.opt configs/example/fs.py --detailed --caches
--l2cache -r 1
but I get this error:
info
You'll need to create a disk image as outlined in:
http://gem5.org/Disk_images
and put the android filesystem on it. You should make sure that android
is in the name of the disk image so gem5 appends the correct kernel
command line.
Ali
You should be able to pass the kernel and disk imag
rc_idx), I see incorrect
value like 0x2f2f2f2f2f2f2f2f. The value is never changed regardless of
execution of different instructions.
Ed
On Thu, Sep 15, 2011 at 2:58
PM, Ali Saidi wrote:
Something like cpu->readIntReg(renamed_reg);
Ali
On Thu, 15 Sep 2011 14:44:59 -0400, Edward Kim wrote:
On Sep 15, 2011, at 6:54 PM, Anirudh Sivaraman wrote:
> On Thu, Sep 15, 2011 at 3:06 PM, Ali Saidi wrote:
>> You'll need to create a disk image as outlined in:
>>
>> http://gem5.org/Disk_images
>>
>> and put the android filesystem on it. You should make
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