[gem5-users] 自动回复: explaination about command_window in MemCtrl.py

2021-10-13 Thread 657029715 via gem5-users
已经收到您的来信，非常感谢！I have received your letter, thank you very much!---傅思清    国防科大Siqing Fu     NUDT___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_inter

[gem5-users] 自动回复: Commited instruction count in timing simple cpu

2021-10-13 Thread 657029715 via gem5-users
已经收到您的来信，非常感谢！I have received your letter, thank you very much!---傅思清    国防科大Siqing Fu     NUDT___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_inter

[gem5-users] 自动回复: SPEC 2017 Benchmarks: Input Files Not Found

2021-10-16 Thread 657029715 via gem5-users
已经收到您的来信，非常感谢！I have received your letter, thank you very much!---傅思清    国防科大Siqing Fu     NUDT___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_inter

[gem5-users] 自动回复: Error with syscall 318 for gem5, when executing with a multi agent reinforcement learning algorithm

2021-10-18 Thread 657029715 via gem5-users
已经收到您的来信，非常感谢！I have received your letter, thank you very much!---傅思清    国防科大Siqing Fu     NUDT___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_inter

[gem5-users] How to specify the operation time setting of a custom instruction

2021-10-29 Thread 657029715--- via gem5-users
Hi all, I've added custom instructions to the RISC-V ISA by modifying the contents of/src/arch/riscv/ISA/decoder and it works properly. But I want to know how to specify the operation time setting of a custom instruction, such as specifying which functional unit it executes in and how many cycl

[gem5-users] Re: Instruction execute stage clock cycles in MinorCPU

2021-10-29 Thread 657029715--- via gem5-users
Hi Volkan, I've noticed that you've been working on RISC-V in gem5 and I'd like to ask you some questions. I've added custom instructions to the RISC-V ISA by modifying the contents of/src/arch/riscv/ISA/decoder and it works properly. But I want to know how to specify the operation time settin

[gem5-users] 自动回复: fatal: Number of ISAs (1) assigned to the CPU does not equal number of threads (2).

2021-11-01 Thread 657029715 via gem5-users
已经收到您的来信，非常感谢！I have received your letter, thank you very much!---傅思清    国防科大Siqing Fu     NUDT___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_inter

[gem5-users] Re: --Script parameter cannot be used

2020-11-10 Thread 657029715--- via gem5-users
Hi Gabe： I compiled the m5 utility, do you know how to call it to work? blessing you. Siqing Fu 657029...@qq.com From: Gabe Black via gem5-users Date: 2020-11-10 07:30 To: gem5 users mailing list CC: -17; Gabe Black Subject: [gem5-users] Re: --Script parameter cannot be used The --script opti

[gem5-users] How the big and LITTLE cores are modeled？

2021-03-20 Thread 657029715--- via gem5-users
Hi all: In configs/common/cores/arm, we can see the ex5_LITTPE and EX5_big core models, which inherit from MinorCPU. What I want to know is whether the modeling of these two models is explained in corresponding documents or papers. For example, MinorCPU actually implements a 4-stage pipelin

[gem5-users] How to modify opLat of MinorCPU？

2021-03-21 Thread 657029715--- via gem5-users
Hi all: I recently had a problem adjusting the MinorCPU parameters. I tried to modify the oplat in FU, but the changes to the parameters did not change the statistical results. Does anyone know what prevented me from modifying the oplat executed by the instruction? Thanks and regards Siqing Fu