Hi,
I am trying to run a RISC-V FS simulation in gem5 using the provided
kernel and image, but the system seems to get stuck at login (see below).
At first, I thought there was something wrong with my simulation script,
but then I tried to run the example
(configs/example/gem5_library/riscv-
Hi
Below are commands and log info of the error mentioned in the subject line.
Info of workload is:
>file demo.elf
demo.elf: ELF 64-bit LSB executable, ARM aarch64, version 1 (SYSV),
statically linked, with debug_info, not stripped
>build/ARM/gem5.opt configs/learning_gem5/part1/two_level.py
com
Hi ikram,
On 01/02/2023 10:19, IKRAM via gem5-users wrote:
Hi
Below are commands and log info of the error mentioned in the subject line.
Info of workload is:
file demo.elf
demo.elf: ELF 64-bit LSB executable, ARM aarch64, version 1 (SYSV), statically
linked, with debug_info, not stripped
Hello,
I am trying to run the dhrystone benchmark (from this repo:
https://github.com/riscv-software-src/riscv-tests) on RISCV bare-metal
mode using gem5 in full-system simulation model (fs_linux.py). I have
compiled the dhrystone code using riscv64-unknown-elf-gcc compiler.
When I run this, the si
Hi Soramichi,
I agree with the change you are proposing.
May I open an issue on Jira on this and assign myself?
Yes, please do that.
-Ayaz
On Tue, Jan 31, 2023 at 11:07 PM Soramichi Akiyama
wrote:
> Hi Ayaz,
>
> thank you for your reply and I really appreciate your effort for making
> SMT w
Another thing to notice is that the current PCID change is intended for SE
mode only (as you might have seen in the comments of the JIRA issue:
https://gem5.atlassian.net/browse/GEM5-332). So, the global bit probably
would not be used anyways.
-Ayaz
On Wed, Feb 1, 2023 at 4:14 PM Ayaz Akram wrot
