[gem5-users] Set number of register file read and write ports

Hi, I'm trying to check the influence of the number of read and write register file ports on the maximum IPC achieved by the OoO model. However, I could not find any parameter that models the number of register file ports. Is there any? For example, in none of the methods chain: readIntRegOpera

[gem5-users] Re: Set number of register file read and write ports

Hi, Based on my understanding of O3CPU, I think your assumption is correct. However, probably parameters like issueWidth and wbWidth can be used to control maximum register read/writes indirectly. -Ayaz On Tue, Jan 17, 2023 at 3:32 AM pedro--- via gem5-users wrote: > Hi, > > I'm trying to chec

[gem5-users] Re: Query about Support for Chiplet Architecture

Hi Zhengrong, On Thu, Jan 12, 2023 at 2:40 PM Zhengrong Wang via gem5-users < gem5-users@gem5.org> wrote: > Hi All, > > Our group has been using gem5 for architecture research for a long time, > and we currently want to explore some ideas on modern multi-chiplet > architectures, e.g. AMD's EPYC.