[gem5-users] L1 Data Cache Ports

Hi. I am looking for a way to model and assess the impact of having one vs. two ports in the L1 data cache (e.g., cache serving two loads in the same cycle). I found two variables "*cacheLoadPorts*" and "*cacheStorePorts*", which are both set to 200 (surprinsingly) by default. There was some dis

[gem5-users] Re: Ruby: Connect rubyport and CPU through crossbar

Hi Wilson,\ \ I’ve never tried that myself but I believe that the issue comes from RubyPort::MemResponsePort::getAddrRanges() always returning an empty list, making the XBar believe that the ruby_system is not responding to any address. That would require a fix likely going through RubySystem to