As a follow-up on this, I saw that in the config.dot and config.ini files
generated in the m5out folder, there is only 1 memory controller in the case of
dGPU but different memory pools for the CPU and dGPU.
In that case, what is the real difference between APU and dGPU?
Usually, host-to-device (
Hi,
You basically have an address map or controller hierarchy specification issue.
CHI uses a different address to machineID mapping scheme than previous
protocols. CHI adds the concept of "downstream machine" in the sense of
"downstream in the memory hierarchy". When calling
AbstractControlle
Hi Sampad,
I don't think that you can import C++ enums in SLICC in a general and sage way.
SLICC does not support "external enums" so any enum declared in SLICC will
result in a C++ enum being generated under the gem5::ruby namespace.
One way of safely using external enums (any namespace, scope
Hi Gabriel,
Thanks for the detailed information. My enum is small, so I think this will
work just fine.
Regards,
Sampad
On Mon, Nov 8, 2021 at 6:43 AM Gabriel Busnot via gem5-users <
gem5-users@gem5.org> wrote:
> Hi Sampad,
>
> I don't think that you can import C++ enums in SLICC in a general a
Hello all,
The version of gem5 I am using is 21.1.0.2.
I found that when I initiate a new prefetcher for cache in the CPU model, the
prefetcher cannot connect to the cache. And the attribute "prefetcher" of the
cache object is still NULL.
For example, I use the O3_ARM_v7a_3 CPU model to run SE s
