[gem5-users] Fatal when using ARM config file with walk cache

Hello, When using configuration files that define a walk cache (configs/common/cores/arm/O3_ARM_v7a.py and configs/common/cores/arm/HPI.py for example), I get the following error: fatal: Port .cpu.itb_walker_cache.cpu_side is already connected to .cpu.mmu.itb_walker.port, cannot connect .cpu.m

[gem5-users] Re: Fatal when using ARM config file with walk cache

Hi Nathanael, this is a know problem in develop that will be fixed in next release. It comes from the fact that we are using 4 table walkers (for S1I-TLB, S1D-TLB, S2I-TLB and S2D-TLB). I am currently working on: a) Implementing a VA indexed walk cache replacing current PWCs (.gem5 _walker_cac

[gem5-users] Re: Fatal when using ARM config file with walk cache

Hi Giacomo, Thanks for your answer. Then, can I keep the two lines commented out for the moment? Should I expect negative impact from that? Thanks, Nathanael Premillieu -Original Message- From: Giacomo Travaglini [mailto:giacomo.travagl...@arm.com] Sent: Tuesday, October 19, 2021 4:09

[gem5-users] How to build custom disk images

Hello, As for I am not familiar with the gem5. I would like to custom disk images following the gem5.googlesource.com  gem5-resources to make a PARSEC disk image. I followed the instructions as the README.me, but I encounter some errors. The error information is shown as follow: qemu: outp