[gem5-users] Re: Accelerator as PIO device writing back to main memory

2021-09-15 Thread diavastos--- via gem5-users
Giacomo, Answering your questions: 1. No, I build my own config file using the configs/example/apu_se.py as a baseline 2. I have several simple memory objects on the accelerator that connect directly on the membus that then connects to the memory controller. But I have no iobridge between those

[gem5-users] accessing the GEM5 101 webpages

2021-09-15 Thread Muhammad Aamir via gem5-users
Hi everyone, Does anyone know the backup links for the GEM5 101 links as they are down? I cannot seem to access all of them thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_ur

[gem5-users] Wrong stats in gem5 v21.1

2021-09-15 Thread Chen Meng via gem5-users
Hi all, When I switched gem5 from v21.0.0.0 to v21.1.0.1, the dumped `stats.txt` is much longer than previous one, filled with strange entry like the following. ==stats.txt (Trimmed)== system.cpu0.dcache.demandHits::cpu0.mmu.dtb.walker 730151 system.cpu0.dcache.demandHits::cpu0.m

[gem5-users] gem5 Power Model

2021-09-15 Thread Victor Kariofillis via gem5-users
Hi, I have some questions about the power model in gem5. - In what extent is it implemented? I'm mainly interested in a power model for the CPU. Is there one? - I have seen a python configuration script (fs_power.py) for ARM. Is there a power model only for the ARM architecture? - If yes, can it

[gem5-users] How to extract instruction traces

2021-09-15 Thread Scott Blankenberg via gem5-users
Dear all, I was wondering if there was an easy way to extract the instruction traces for a given benchmark using GEM5. If so, is there a tutorial on how to do so? Or any other pointers someone could give me? Going through the GEM5 documentation, I have not found a straight-forward way yet. I