[gem5-users] CHI and Ruby Cache block size

Hello I am using the CHI protocol with Ruby. The CHI L1 Cache and L2 Cache are derived from the RubyCache class model. My question: Within Ruby, is it possible to have different cache line size for the L1 and L2 caches? I had a look at src/mem/ruby/structures/RubyCache.py and there is only bl

[gem5-users] Re: SE ARM: Assertion error in rename_map.hh on call to pthread_create using m5threads

Here is the complete Exec trace as well, running it with --debug-flags=Exec: https://gist.github.com/Icohedron/4d1fef84b4266a5945cb707ab990bde4 On Sun, Aug 15, 2021 at 10:48 PM Deric Cheung wrote: > I wrote a small program to test pthreads using the m5threads library on an > ARM O3CPU using sysc

[gem5-users] Re: SE ARM C stdio fseek() function invokes a failed writeBlob in port_proxy.hh

Using --debug-flag=Exec I have also produced an execution trace of the binary: https://gist.github.com/Icohedron/1920d7b0130d8348d509038a10122c23 On Sun, Aug 15, 2021 at 6:46 PM Deric Cheung wrote: > I'm trying to write and run some file IO code for ARM, but I encounter a > fatal error when tryi