[gem5-users] Single Core SMT on DerivO3CPU

Hi folks, I'm kinda new to Gem5. I'm trying to see the impact of the hardware threads number on a single-core x86 system performance. So I'm trying to use DerivO3CPU with smtNumFetchingThreads > 1 (1 is the default value). While the default value works fine, I'm getting weird errors when

[gem5-users] illegal instruction in RISCV mode

Hi, all I use the latest v21.1 gem5 to run RISCV simulation, using the workloads provided by gem5-resources but for a simple simulation like this: ./build/RISCV/gem5.opt configs/example/se.py -c qsort.riscv there will be a panic as below "panic: Illegal instruction 0x3002a073 at pc 0x800

[gem5-users] Re: Circular Buffer Error with O3_ARM_v7a

Hi all, Sam, did you figure out what the problem was, or did anybody else solve it? I am also getting the same error and any help would be appreciated. I am running my simulations in SE mode, ARM ISA, and using the O3 processor. Best Ange ___ ge

[gem5-users] Re: 答复: gem5 v21.1 released!

Hi Liyichao, We welcome contributions to the gem5 resources! Currently, we have full system resources available for x86 and one available for RISC-V. We don't have any Arm resources available right now, but that's only because we haven't had the time (or resources ;)) to get around to it. Again, w

[gem5-users] Does a write request to cache block subsequent ones?

Hi, I am curious about the process of writing to classical cache. I have found some parameters related, like `fillLatency`, `forwardLatency`, `dataLatency` and `lookupLatency` in BaseCache. However none of these ones impact the subsequent requests. For instance, `fillLatency` only relates to