Hi all,
I've encountered a problem when setting the timing parameters of cache.
I noticed before the latency to read/write a cache was separated by dataLatency
and fillLatency in BaseCache. But when I was tuning the parameters for both, it
seems to have little effect for overall cache miss late
Hi,
If your stats are for the run from the beginning to the end, sim_ticks in
the stats file is the benchmark's execution time in your simulated system.
Jiayi
On Wed, May 26, 2021 at 1:36 AM VAIDYA ROHINI VILAS via gem5-users <
gem5-users@gem5.org> wrote:
> Hello,
> I want to calculate CPU exec